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 Skylake/Kaby/Coffee/Comet/Rocket Lake OC V1, Show off your OC here

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TSowikh84
post Jul 3 2021, 06:49 PM

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QUOTE(llaw @ Jul 3 2021, 05:57 PM)
Joining the Samsung B-die club now tongue.gif

2x16GB Acer Predator Apollo (Samsung B-Die DR) 4266MHz 17-18-18-38 @ 1.55V Gear2
Initial finding is this RAM kit max can reach till 4266MHz without any error, 4400MHz onwards will have error even with loosen timing or increased voltage.
Slightly harder to get it stabilized compared to Hynix DJR kit.
*
Nice!
1.50V can or not?
Try to match this B-die DR kit biggrin.gif https://www.gskill.com/specification/165/29...B-Specification
llaw
post Jul 3 2021, 09:30 PM

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QUOTE(owikh84 @ Jul 3 2021, 06:49 PM)
Nice!
1.50V can or not?
Try to match this B-die DR kit  biggrin.gif https://www.gskill.com/specification/165/29...B-Specification
*
Unfortunately cannot, got error sad.gif

user posted image

My kit is only rated at 3600MHz 14-15-15-35 @ 1.45V
So the G.Skill 4266C17D has to be higher bin.
llaw
post Jul 4 2021, 12:38 AM

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Another tweak. Trying to 'fix' the RTL value because I noticed that upon cold boot, the RTL may change between these 2 values: 45/45 or 45/46
If boots up with RTL 45/45, then passing TM5 memtest. However, if it boots up with RTL 45/46, will fail TM5 memtest with single error on test #2. No other parameters change except this.

Strangely on this mobo, I can't seem to change the RTL value directly. Have to set RTL training to enable under memory training page to get the RTL value to be fixed. And with this, I got a lower RTL value of 40/41 instead.

With this lower RTL value, I need to bump up the RAM voltage a bit more to 1.57V to be error free. Good thing is, I got to shave off 2ns of latency. biggrin.gif

user posted image
TSowikh84
post Jul 4 2021, 08:36 AM

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QUOTE(llaw @ Jul 4 2021, 12:38 AM)
Strangely on this mobo, I can't seem to change the RTL value directly.  Have to set RTL training to enable under memory training page to get the RTL value to be fixed.
*

Yeah you're right, manual RTL doesn't work on Z590.

llaw
post Jul 4 2021, 09:09 AM

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QUOTE(owikh84 @ Jul 4 2021, 08:36 AM)
Yeah you're right, manual RTL doesn't work on Z590.
*
So it's a known issue for Z590?
TSowikh84
post Jul 4 2021, 09:34 AM

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QUOTE(llaw @ Jul 4 2021, 09:09 AM)
So it's a known issue for Z590?
*
Yes, not a big problem as you can enable that RTL training in algo page like you already done.
llaw
post Jul 4 2021, 02:26 PM

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Lowest latency I can get:

user posted image

But not stable though... just for the benchmark number tongue.gif
Bonchi
post Jul 7 2021, 02:25 PM

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QUOTE(llaw @ Jul 4 2021, 02:26 PM)
Lowest latency I can get:

user posted image

But not stable though... just for the benchmark number tongue.gif
*
32GB? try go command rate 2T. probably can go higher. Yours looks like it's limited to the IMC.
llaw
post Jul 7 2021, 11:35 PM

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QUOTE(Bonchi @ Jul 7 2021, 02:25 PM)
32GB? try go command rate 2T. probably can go higher. Yours looks like it's limited to the IMC.
*
I'm running Gear2, so naturally the command rate will be 1T. Never try 2T on Gear2 before, I bet the performance will suffer.
llaw
post Jul 7 2021, 11:40 PM

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Just found out that on RocketLake CPU, *_dd and *_dr is reversed compared to CometLake.
Since I'm running only 1 stick of RAM per channel, I should be able to drop *_dr = 0

Getting pretty much similar AIDA number compared to previously when *_dd == *_dr ... noticed latency drop just a little bit, perhaps placebo effect tongue.gif

user posted image
Bonchi
post Jul 7 2021, 11:41 PM

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QUOTE(llaw @ Jul 7 2021, 11:40 PM)
Just found out that on RocketLake CPU, *_dd and *_dr is reversed compared to CometLake.
Since I'm running only 1 stick of RAM per channel, I should be able to drop *_dr = 0

Getting pretty much similar AIDA number compared to previously when *_dd == *_dr ... noticed latency drop just a little bit, perhaps placebo effect tongue.gif

user posted image
*
ah right, forgot you're on 11th lol. laugh.gif
maybe up the trfc and loosen the RTL. you dont really gain very significant latency from there. better to tighten the primary first then only push the secondary.

This post has been edited by Bonchi: Jul 7 2021, 11:43 PM
llaw
post Jul 7 2021, 11:51 PM

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QUOTE(Bonchi @ Jul 7 2021, 11:41 PM)
ah right, forgot you're on 11th lol. laugh.gif
maybe up the trfc and loosen the RTL. you dont really gain very significant latency from there. better to tighten the primary first then only push the secondary.
*
Urghh... unfortunately this mobo doesn't allow me to hand-tweak the RTL/IOL. Not 100% sure if it's mobo problem or 11th gen problem or combination of it.
I can only force the RTL to change by enabling RTL training BIOS setting.
Bonchi
post Jul 8 2021, 12:22 AM

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QUOTE(llaw @ Jul 7 2021, 11:51 PM)
Urghh... unfortunately this mobo doesn't allow me to hand-tweak the RTL/IOL.  Not 100% sure if it's mobo problem or 11th gen problem or combination of it.
I can only force the RTL to change by enabling RTL training BIOS setting.
*
cant hand tweak but i think owikh shown before in some older posts where to set so that you can set a base for the memory to train from. Well you mobo is a pretty good one. such high read lol. Mine only manages read 61K but my write is at 66K (MSI crappy bios).
cstkl1
post Jul 8 2021, 01:30 AM

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QUOTE(llaw @ Jul 7 2021, 11:40 PM)
Just found out that on RocketLake CPU, *_dd and *_dr is reversed compared to CometLake.
Since I'm running only 1 stick of RAM per channel, I should be able to drop *_dr = 0

Getting pretty much similar AIDA number compared to previously when *_dd == *_dr ... noticed latency drop just a little bit, perhaps placebo effect tongue.gif

user posted image
*
odd pairing

llaw
post Jul 8 2021, 10:12 AM

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QUOTE(Bonchi @ Jul 8 2021, 12:22 AM)
cant hand tweak but i think owikh shown before in some older posts where to set so that you can set a base for the memory to train from. Well you mobo is a pretty good one. such high read lol. Mine only manages read 61K but my write is at 66K (MSI crappy bios).
*
Unfortunately I didn’t manage to get it to work. Either default or RTL training enabled with lower value.
Any manual value that I put seems to be ignored.
llaw
post Jul 8 2021, 10:13 AM

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QUOTE(cstkl1 @ Jul 8 2021, 01:30 AM)
odd pairing
*
Care to enlighten which one is odd?
Bonchi
post Jul 8 2021, 11:28 AM

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QUOTE(llaw @ Jul 8 2021, 10:12 AM)
Unfortunately I didn’t manage to get it to work.  Either default or RTL training enabled with lower value.
Any manual value that I put seems to be ignored.
*
well, generally it's better for the bios to train the values anyways. Dont think Asus will retrain like MSI which will ruin all the effort at random.

Well, as explained by owikh before. the trained RTL value is affected by SA/IO/DIMM voltages (too high or too low) and all the timing values... so if not done right, the RTL IOL will be weird. Thus it can be a sign of instability.
you do have some odd settings such as the 4 TRDWR values ideally should be all same, like 12-12-12-12.

i think what ctskl say weird is that although you fulfilled the rule to not be more than 1 apart but it normally looks like this:

CHA D0 40
CHA D1 41

CHB D0 40
CHB D1 41

cant see your IOL to judge further.
Maybe you can copy some of those sifu's values and try. Your mobo is pretty similar to theirs, maybe can even ask for a bios profile. Im pretty sure they are willing to share.

also bdie you can get away with lower SA/IO/DIMM voltages so sometimes having them too high following from your previous DJR settings, it may cause instability. try 1.4v-1.45 for 4266.. also Bdie is quite temp sensitive so the quality of the ram's heatsink matters too (which is why TridentZ does quite well).

This post has been edited by Bonchi: Jul 8 2021, 11:34 AM
llaw
post Jul 8 2021, 03:53 PM

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QUOTE(Bonchi @ Jul 8 2021, 11:28 AM)
well, generally it's better for the bios to train the values anyways. Dont think Asus will retrain like MSI which will ruin all the effort at random.

Well, as explained by owikh before. the trained RTL value is affected by SA/IO/DIMM voltages (too high or too low) and all the timing values... so if not done right, the RTL IOL will be weird. Thus it can be a sign of instability.
you do have some odd settings such as the 4 TRDWR values ideally should be all same, like 12-12-12-12.

i think what ctskl say weird is that although you fulfilled the rule to not be more than 1 apart but it normally looks like this:

CHA D0 40
CHA D1 41

CHB D0 40 
CHB D1 41

cant see your IOL to judge further.
Maybe you can copy some of those sifu's values and try. Your mobo is pretty similar to theirs, maybe can even ask for a bios profile. Im pretty sure they are willing to share.

also bdie you can get away with lower SA/IO/DIMM voltages so sometimes having them too high following from your previous DJR settings, it may cause instability. try 1.4v-1.45 for 4266.. also Bdie is quite temp sensitive so the quality of the ram's heatsink matters too (which is why TridentZ does quite well).
*
The RTL values are from the MRC training algorithm. I just assume it’s optimized and I can’t manually override it anyway.
If I set tRDWR_* to be all 12, I got error in TM5, so I increase some of it.

And you’re right that I’m running higher voltage than usual B-die kit needs. So I’m going to retune everything on lower voltages later.
Also, my RAM is definitely running hot as my thermal probe reads 51C at heatsink area so memory chip will definitely be higher. Not enough space to mount a fan, unless removed side panel and get a fan to blow it directly - not practical doh.gif
Bonchi
post Jul 8 2021, 04:07 PM

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QUOTE(llaw @ Jul 8 2021, 03:53 PM)
The RTL values are from the MRC training algorithm. I just assume it’s optimized and I can’t manually override it anyway.
If I set tRDWR_* to be all 12, I got error in TM5, so I increase some of it.

And you’re right that I’m running higher voltage than usual B-die kit needs. So I’m going to retune everything on lower voltages later.
Also, my RAM is definitely running hot as my thermal probe reads 51C at heatsink area so memory chip will definitely be higher.  Not enough space to mount a fan, unless removed side panel and get a fan to blow it directly - not practical  doh.gif
*
yeah this kind of settings have to find sweet spot, cannot simply brute force. especially by cranking up voltage.

Sometimes your kit will also will not like certain ranges. Like my B-die struggle to get to 4133 17-17-17-37 as that was my initial target. already put voltage to 1.5V but it just cannot post... brute force the training then will be super unstable anyways. But then 4266 17-17-17-37no issues at 1.4V doh.gif rock stable.

maybe you can try skip 4266 to 4500 to tune.
llaw
post Jul 8 2021, 09:03 PM

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QUOTE(Bonchi @ Jul 8 2021, 04:07 PM)
yeah this kind of settings have to find sweet spot, cannot simply brute force. especially by cranking up voltage.

Sometimes your kit will also will not like certain ranges. Like my B-die struggle to get to 4133 17-17-17-37 as that was my initial target. already put voltage to 1.5V but it just cannot post... brute force the training then will be super unstable anyways. But then 4266 17-17-17-37no issues at 1.4V  doh.gif rock stable.

maybe you can try skip 4266 to 4500 to tune.
*
Now I’m trying similar as yours: 4266 17-17-17-37 @ 1.5V and loosen a bit secondary/tertiary timings.
So far looks doable, need to run all tests to ensure stability. Can’t do lower than 1.5V else will error out easily.

Previously I did try higher speed like 4400 and 4533. 4400 still possible but need to relax the timing quite a lot but 4533 no boot. So I think 4266 is the best bet for long term stability.

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