LIBRARY ieee;
USE ieee.std_logic_1164.all;


ENTITY reg_test IS
PORT ( INIT, M20 : IN STD_LOGIC;
MUL0, MUL1 : IN STD_LOGIC;
CLK, Ca : IN STD_LOGIC;
AO : IN STD_LOGIC_VECTOR (1 to 7);
eno : OUT STD_LOGIC;
M0 : OUT STD_LOGIC_VECTOR (0 to 7));
END ENTITY;


ARCHITECTURE r OF reg_test IS

SIGNAL d : STD_LOGIC_VECTOR (0 to 7);
SIGNAL q : STD_LOGIC_VECTOR (0 to 7);
SIGNAL en : STD_LOGIC;
SIGNAL notM2: STD_LOGIC;

COMPONENT d_ff_en IS
PORT ( d, clk, en : IN STD_LOGIC;
q, q0 : OUT STD_LOGIC );
END COMPONENT;


BEGIN
en <= NOT(INIT AND MUL0 AND MUL1);
notM2 <= NOT M20;

d(0) <= (INIT AND M20 AND AO(1)) OR (INIT AND notM2 AND q(1));
d(1) <= (INIT AND M20 AND AO(2)) OR (INIT AND notM2 AND q(2));
d(2) <= (INIT AND M20 AND AO(3)) OR (INIT AND notM2 AND q(3));
d(3) <= (INIT AND M20 AND AO(4)) OR (INIT AND notM2 AND q(4));
d(4) <= (INIT AND M20 AND AO(5)) OR (INIT AND notM2 AND q(5));
d(5) <= (INIT AND M20 AND AO(6)) OR (INIT AND notM2 AND q(6));
d(6) <= (INIT AND M20 AND AO(7)) OR (INIT AND notM2 AND q(7));
d(7) <= (INIT AND M20 AND Ca);

g0 : d_ff_en PORT MAP (d(0),clk,en,q(0));
g1 : d_ff_en PORT MAP (d(1),clk,en,q(1));
g2 : d_ff_en PORT MAP (d(2),clk,en,q(2));
g3 : d_ff_en PORT MAP (d(3),clk,en,q(3));
g4 : d_ff_en PORT MAP (d(4),clk,en,q(4));
g5 : d_ff_en PORT MAP (d(5),clk,en,q(5));
g6 : d_ff_en PORT MAP (d(6),clk,en,q(6));
g7 : d_ff_en PORT MAP (d(7),clk,en,q(7));

M0(7) <= q(7);
M0(6) <= q(6);
M0(5) <= q(5);
M0(4) <= q(4);
M0(3) <= q(3);
M0(2) <= q(2);
M0(1) <= q(1);
M0(0) <= q(0);

eno <= en;

END r;