Your adder and subtractor circuit using XOR? (X-ATAU i suppose in BM )

Just a bump to keep it alive. Currently doing Control Unit, dunno need how long to finish 8-}

Damn, I need to use gate level oso, behavioral no syiok

Phew... I'm used to work for dunno how many days for my Final Year Project, so damn tired to be on schedule. Ikan genius man, 4 minutes can finish a project

Hey, send me your CU design, see which part i can leech u (if u dun mind)

edit : still got some headache in implementing Interrupt Request into the CU.

This post has been edited by charge-n-go: Oct 17 2005, 07:16 PM

Registration done

This post has been edited by charge-n-go: Oct 23 2005, 10:24 PM

alrites, thanx for reporting. I got another source of information if I dunno something


oops, computer hardware is more related to e&e ma. Maybe u can ask almostthere to open mecha engineering thread in fast & furious

Added you, welcome !
Usually i buy my parts in SS2 bcoz near my house, lazy to go so far

anybody has good slides on the algorithm about Manchester Carry Chain adder? I found a lot from google, but most of them are talking about transistor optimization (which i never learn b4 ). I only got a lil tips tat Manchester is using some carry skip and carry lookahead method to speed up the process.

Implementation : 4x 8-bit adder for halo's FADD unit. Need a small, low power and decent speed adder. From some graph i found manchester suits this, anymore recommendation about which adder to be used?

Thanx a lot

I already have a couple of CL and CR hybrid. Just wanna try if MCC or some Carry Skip can give me good results for 8-bit

halo, maybe can ask shabiul for help (JKJK). According to martianunlimited suggestions previously, i already have a few 8-bit adders for you. Choose one to suit yr multi adder FP unit design, hehehe.


btw, anybody knows how to calculate the delay due to the increase of fan-in? Thanx

icic, thanx. how bout normal OR and AND gates? Well, I js wondering if there's any formula to calculate the delay.

In my design, I can only estimate how many gate delays a signal has. Sometimes the signal propagates through a few big fan in gate, which i think it might have 2x delay than a normal 2 input gate. Just hoping to have more precise calculation.

yeap, shabiul islam LOL. He shot me a lot during my presentation, luckily can answer his Qs.

Fabian still around, he's supervising ppl on robotics. Seems like u r from MMU too, haha.

My biggest fan-in is 9 (for 8th bit CLA adder), and no big fan out

May i know where to get the STA? Any recommendation? Lanun edition maybe we can PM each other

Thanx ya

MMU eat so much $ liao still not willing to pay the software?
Well, I actually separated into 2x 4-bit CLA, so the max fan in will be OR5. I'll try to search those software in LYP next week. Thanx !

I also have 2-2-2-2 (2-bit CLA rippled together) and 2-3-3. The problem is when shabiul become my moderator, he was requesting me to give the delays and size of each adder and compare them. After that only we choose the most appropriate one.
That's the reason i really need to know the delays precisely, as measuring on 'gate delay' in general is too rough in calculation. My supervisor Dr Ajay also wants us to compare different design and choose one of the best for my 8-bit CPU. FYI, I'm designing custom chip with gate level optimization rather than using FPGA

Hmm..... do u know any sites have this kinda statistic.
I only have a book borrowed from halo. Max fan in is up to 4 input only (AND, OR, NOR, NAND). Don't even have the 3 input XOR for the adder. I've searched through google and get a database on gate size and power consumption only. Can't find the delay though

Pspice? wow, tat's too time consuming
I still got many things to work on like VHDL and better gate optimization. Sigh, FYP is really tough.

Thanx for all the feedback


*fishy then how r u doing delay analysis without those tools? manual calculation?

This post has been edited by charge-n-go: Nov 7 2005, 10:11 AM

thanx dude. So all the software u mentioned js now is from yr uni? You don't have any copies in yr comp kah?

This post has been edited by charge-n-go: Nov 7 2005, 12:29 PM

omg.. then I'm having big problem in deciding the delay, hahaha.

Well, trying to use VHDL and Max Plus 2 to determine, dunno if this method can work or not. Yesterday I've done, but the input and output seems to occur at the same time LOL.

Thanx X10A (or should i call u X20A )

I've got myself a database.

NAND2 : 1.4ns , 4 tr
NAND3 : 1.8ns , 8 tr
NAND4 : 2.2ns , 10tr

AND2 : 2.4ns, 6tr
AND3 : 2.8ns, 8tr
AND4 : 3.2ns, 10tr

Isit correct if i assume:
1. NAND5 having 2.6ns delay and 14 transistors?
2. AND5 having 3.6ns delay and 12 transistors?

Thanx !

This post has been edited by charge-n-go: Nov 10 2005, 11:46 AM

LoL, near 10 years ago (1997). Damn, never notice that in the beginning !
Principles of Digital Design by Daniel D Gajski, Uni of California.

I'll email my supervisor to ask about it next week bcoz he is still on holidays. Thanx for yr kind help dude

wow, tat's a lot of work. It's ok if u r busy.

Well, later might need yr full name to be in my project report
Hope my lecturer accept my proposal, will inform u a.s.a.p.

btw, do u know any books have this kind of figures? Maybe i can js get from there and save your hassles.

David83, got try google-ing? I always find plenty of info there.

ikanayam, that's the 1st time i see this diagram,hahaha.
Well, engineering is the combination of science and art. Without creative mind we can't even come out a simple design. K7 and K8 architecture is an art man, we are going to see another masterpiece - Conroe next year

haha, what about doing the whole CPU?