Today js changed my 8-bit adder's VHDL from structural coding to behavioral coding. It is Sooooo much faster with behavioral and save a lot of troubles portmapping

Well, behavioral is just 2.4ns (including the buffer register at the adder output), but the structural circuit without the buffer register already have 8.1ns delay and a lot of glitches.

I use structural in the 1st place to generate my custom adder, well of course it screwed up bcoz the CPLD might not have some predefined LUT or Cell for tat purpose. Fishy i still like the ASIC leh, kinda cool to have everything start from scratch and slowly fine tune. Argghh... still angry y my uni doesnt have the Cadence tool

I'm using Altera MaxPlus 2 with Max7000B CPLD

This post has been edited by charge-n-go: Apr 3 2006, 10:25 AM

I've tried various methods, behavioral still the best

Human optimization lost to compiler optimization, damnit

Left 14 days before report submission for my CPU. I hate documentation !!

I'm simulating with Maxplus 2, but final implementation will be in Spartan 3 Starter Kit CPLD. Still waiting for its arrival

I'm not sure if the VHDL code can be transferred to Xilinx successfully. THeoretically its possible la, but still scared ler

Tat's what I'm afraid of. It may work flawlessly and fast enough in Max7000B, but when it is synthesize in Spartan 3, maybe got minor glitches during the positive clock edge, then die liao

Well, js pray i can successfully transfer it, if not presentation time will kena from moderator

btw X10A Freedom, where r u studying? May i know where u got the tools to construct yr butterfly layout?

oh.. KBU got mentor graphic, but MMU doesnt have ler
I tried to find lanun in LYP, found nothing. hahaha.

btw, do u got any jobs after graduation?

ahah, it's called the computer engineering thread, sure more on digital stuff la

wanna talk about digital signal processing? DFT and FFT anyone?

X10A Freedom: Altera questions arent that hard. If u hv done layouting b4, it should b easy for u. I've tried and confident but end up not called for interview, js bcoz I'm not 1st class student

hmm... where r u working now ar?
well, my answer is same as my fren (we sit side by side n compare la), but he was called not me, moreover we apply for the same job position
so i suspect is my CGPA ler, he is way higher than me


U mean ASIC? AFAIK, they only want experience engineer or fresh grad in this kinda field, maybe u can la since u did layouting

welcome [ r u g a ].


ERmm.. anyone knows how to extract certain bit from 'add' function?

Let's say,

SIGNAL a,b : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL reg : STD_LOGIC_VECTOR (7 DOWNTO 0);

reg <= (a + b) from 15 downto 8.

What i mean is i need info from the added result A+B (bit 8 to bit 15) into reg. How can I actually do it in 1 clock only?

Thanx

This post has been edited by charge-n-go: Apr 4 2006, 05:01 PM

I've tried this actually:

add_result <= A+B;
reg <= add_result( 15 downto 8);

But using this method, A+B will be stored in add_result upon clock, and the previous clock add_result will be input into reg.

Actually i need the result immediately during current clock, tat's wat i meant by 1 cycle


Ya, there's no such thing as from 15 downto 8, js my description

If u wanna shift b4 add, can make it this way:
reg <= ('0' & a(7 downto 1)) + ('0' & b(7 downto 1))

Well, imho, sometimes 1 clock means that must be in 1 instruction line, and sometime it is not necessary.

Let's say :
IF (clk'EVENT AND clk='1')
a<=b;
c<=d;

^ this one can finish in 1 clock.

however,
IF (clk'EVENT AND clk='1')
a<=b;
c<=a;

^ this one will finish in 1 clock too, but c<=a is taking the A value on previous clock instead of value from latest B value.

i tried b4, but the result isnt correct.

THis is actually my code description:




Anyway, welcome e-jump

I dont think can update if there is no clock

This post has been edited by charge-n-go: Apr 4 2006, 09:40 PM

Outside process statement ar. I nv tried, that
I just put it in process, but included in the ELSE branch (else when no clock signal then reg <= add_result (15 downto 8);

I think maybe I should construct another CASE statement out of the process and try again. Thanx for all yr help


Hmm... i think i'll try agian, maybe some other parts are wrong

haha, i got 1 level sensitive transistor, but never use it bcoz it's pretty useless

My fren tried, but not really working
nvm, i'll try another method.

thx everybody for helping.


i only learnt about 0 resistance, which happens to superconductor at very very low temperature. -ve resistance? i need somebody to enlighten me too

hahaha, i think we learnt a bit too in physical electronics. I oso forgotten liao


Negative differential resistance means, the resistance value is decreasing over time mah, rite?
0 resistance is ideal, and super conductors only has very very near to zero resistance.

-ve resistance is like..... the object exist to have some energy supply (instead of resisting, it is giving energy).

This post has been edited by charge-n-go: Apr 6 2006, 11:23 PM

LoL, i were u, i oso dunno wanna laugh or cry towards this senior

Well, if he said -ve terminal then logical la, -ve resistance is stooopig.

Yes, finally done with my 8-bit CPU FYP. It is working !!

going to grad liao only u report ar...


What about google?
i think SFG is useful for defining the input/output of a system.

welcome, name added

Hey dude, js read your slide. It is really awesome !!
Well, find 1 day i shall learn all these from u