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This post has been edited by charge-n-go: Dec 19 2006, 11:22 PM

Ok, I'll start this thread with a question

I'm stuck at Carry Select Adder (diagram attached).

1. I wonder what is inside the Carry Propagation Logic to compute the Carry Out.

2. Where is the input port X & Y? I really have no idea.

3. For the 4-bit setup (0-3), how the 'Carry' logic works? Is the 1-bit stage linked together via ripple or carry lookahead method?


Thanx for the help !

This post has been edited by charge-n-go: Oct 12 2005, 03:26 AM


Attached thumbnail(s)

Thanx ikanayam. Your design saves some transistor at the setup stage

I was thinking if the setup stage and the Carry logic has something to do with the Carry Look Ahead algorithm.

Setup : P = A+B and G = A.B

Carry Propagate : Cout = P.Cin + G

btw, I need to test on the Carry Select Adder and see how many transistor and the critical path taken for an 8-bit setup, and also if it is bulky when expands to 32-bit in the future. My current design is using two 4-bit CLA link together with ripple carry, i'm afraid when expand it to 32-bit it will be quite slow and bulky.

Here's my CLA + RCA design. The MUX is placed at the input port to select 1 of the 3 sources using the adder (register, multiplier and divider). DEMUX is placed at the output port to do the same function.




Attached thumbnail(s)

Yup, you are correct, DEMUX looks redundant.

Last time i don't have the 'EN' line for other functional units such as multiplier and divider, so hv to use DEMUX to choose the output. This semester i suppose to minimize the gates and critical path, at the same time remains some good speed.

Sigh.. 1st time doing this kinda thing, many problems here and there. I'm sure you are expert liao fishchicken


* Who's studying electronic engineering course pls report in here.
We can help each other in any difficulties in engineering

AFAIK, only a few are taking this course :
ikanayam, silkworm, empire23, winc87, charge-n-go....

Who else, mari mari lapor diri

This post has been edited by charge-n-go: Oct 12 2005, 06:46 PM

Ohh.. really? He's now working or taking master degree? Maybe taking PhD liao, hahaha.

Ya, my multiplier and divider is using the same Adder/Subtractor with some shifting logic.

btw, how's yr ALU going on fishy?

Well, this is the datapath i designed last semester with another team mate.


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icic, nvm. Pls advice us if anything we do is wrong. Added you into the list

Thanx for the advice. I'm not sure if i wanna make into FPGA or not. THe primary goal is to come out a workable design under simulation, secondary is the FPGA implementation on Altera chip.
I've no idea about Convolution Coding Encoder


yup, I'm using Shift Register as input, but not barrel shifter. Multiply and Divide js need to shift 1 bit to left or right, so i js make it to shift when there's a clock. Well, I'm still thinking how to optimize the multiplier bcoz it takes me 16 cycles for an 8-bit MUL.


hehe, wat's CCT?

Here you go ikanayam. That's my logic unit implementation to save some gates and also propagation delay.

The left one is my implementation, the right one is the conventional logic unit using MUX.


Attached thumbnail(s)

lol, i got it now.

anyway, which adder do u think is more appropriate for my design.

8-bit Adder, might be expand to 16-bit or 32-bit in the future. Need to have a balance of power, die size and performance.

Currenly I'm using 2x 4-bit CLA ripple together to be an 8-bit one. I'm not sure if it is efficient enough when scale up to 32-bit.

I have 2 more choices : Carry Select Adder & 1 level CLA.

So which do u think is a better approach?
btw, I still have no idea to start designing a carry select adder, hahaha. Need to figure it out by today.

ikanayam, thanx for yr advice. Well, i think i'll do some research on all kinds of adder. U know what, when i get the material online, cant really understand the transistor leve diagram bcoz i nv learnt b4 (pathetic ler my uni, nv teach )

Hehehe, we got the same taste. I m a noob in physical electronics stuff.

I dunno anything like tat, hahah

btw, here's some stuff i get online


Attached thumbnail(s)

Yeah, but there is very little speed improvement at 8-bit, so don't think I can choose that. The project primary goal is to have a nice adder at 8-bit level, expandable nicely to higher bit is optional actually.

But i think Carry Select is out of question bcoz it's huge and takes a lot of power. Left only with CLA 1 level and my current design (4-bit CLA per block and ripple them together).

alrites, thanx for your advice

I think it's bcoz each IC have an array of same gates, so if we mix the gates, we need a few ICs to construct a circuit. Besides, from one of the book i borrowed from library (not with me now), it says the NAND and NOR gate has lower latency compare to AND, OR and XOR. Well, all these is based on IC design, not sure about FPGA thou.

Thanx draggy for the info, and Ash, u can ask the question here as long as it's related to engineering

Well, that's new info to me

Anyway, do you know how many transistors in AND, OR, NOT and XOR?
Do u know of any good websites about all these things.?

Thanx nutz, winc87 and X10 Freedom.


Sadly, I'm in final year and already taken all the computer subjects (i take it earlier than schedule and push the maths based subj to the final year). My uni (MMU) kinda stupid ler, never teach all these to computer majoring student. I don't even know what is PMOS NMOS circuit like. All i studied is digital logic design and digital computer design for discreet electronics. (all gate level only, and hv to learn VHDL myself). I wonder why i need to take subjects like Analag Comm, Digital Comm (using fourier analysis), electric power system, electrical machine and stuff like that.

Well, i proposed '8-bit CPU' as my final year project title. Already have the basic design except control unit. Now i need to refine and upgrade anything possible 1st before finalize the control unit design. Sigh... it's a tough job.

Anyway, thanx for yr kind advice

This post has been edited by charge-n-go: Oct 13 2005, 09:00 PM

I have another question about the gates.

May i know isit possible to have 5 input per gate? I'm afraid of fan-in problem, bcoz from the book "Princilples of Digital Design' by Daniel Gajski, i see the max of 4 input gates only, don't have 5 input one.

btw, I'm gonna simulate using Altera MaxPlus II, dunno if it support FPGA or not. Sorry for the noob question bcoz I m self learning VHDL and simulator and kinda blur now. Thanx !

erm... actually i mean 5 input per gate

Nope, sorry I've no idea on that. I only know a bit of MaxPlus II


Hmm... thanx for the tips

btw, can i count the delay using conventional way? For example, 2 leg NAND gate has 4ns delay (from the same book mentioned above) and 2 leg AND gate has 6ns. So in FPGA, do the gates having the same delay regardless of the type?

Well, actually i'm using hand drawn (using corel draw actually) to draw out all the gate circuit design, then I'll write the VHDL (using architecture behaviour) in MaxPlus 2. Isit the same as what u meant using the Mentor graphic?
What kind of coding style is more efficient? Behavorial or architecture?


Edit : I have another doubts
If wanna save power when any of the functional unit is idle, can i js use clock gating? Any other implementation besides that? Thanx

This post has been edited by charge-n-go: Oct 14 2005, 01:06 AM

X10 Freedom, thanx for the info



Digital Computer Design has VHDL, but the lecturer didnt really teach, js go through damn quickly. He teaches mainly on the gate level design.

Power Electronics is important, bcoz u need the knowledge to construct power supply unit. Well, Analog Comm, Digital Comm, Intro to power system, Intro to machine and stuff like that is really useless. I hope they can include stuff like IC design and transistor level optimization like what others have told me here.

MMU is using Altera software. I'm not sure about silvaco.



No thanx to DSP, I'm scared of Fourier and other wave equations

This post has been edited by charge-n-go: Oct 14 2005, 06:18 PM

Actually in MMU, we took 'data communication' subject for all the CDMA, transmission (in binary), compression technique and stuff like that. Digital Comm basically is an extension where we learn about how the digital signal is represented in Fourier and how to convert sinc to square function and etc. Then we need to design some filter to select the correct bandwidth, and some stuff like tat, cant really remember liao
Well, if we cant get the FYP topic (like me), I'm proposing my own one, so i guess tat's not an issue