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This post has been edited by charge-n-go: Dec 19 2006, 11:22 PM

Ok, I'll start this thread with a question

I'm stuck at Carry Select Adder (diagram attached).

1. I wonder what is inside the Carry Propagation Logic to compute the Carry Out.

2. Where is the input port X & Y? I really have no idea.

3. For the 4-bit setup (0-3), how the 'Carry' logic works? Is the 1-bit stage linked together via ripple or carry lookahead method?


Thanx for the help !

This post has been edited by charge-n-go: Oct 12 2005, 03:26 AM


Attached thumbnail(s)

To keep things simple, you can just use a adder setups of your choice for the 0-Carry and 1-Carry units (simplest would be a ripple carry adder since the bounding factor will be the latency through the muxes anyway). I am greatly simplifying the design, not using the "Setup" units at all. Refer to the attached picture above for my description.

Basically for each stage (4bits in this case) you have 2 adders, one computing the result for Cin = 0 while the other is computing the result for Cin = 1. The 4 bit output + 1bit Cout from each adder go into the mux which selects which output to use depending on the Cin. So the muxes are 10 bit inputs and 5 bit outputs.

If you already understand what i described, you can of course optimize the design by moving redundant hardware into the Setup unit and separating the "Carry" units as shown in your picture.

Your picture is not exactly intuitive. The muxes are not exactly at the same level time wise (if you imagine the actual circuit working). This is because the C4 is actually a result coming out from the 1st mux. C8 is the carry result coming out from the 2nd mux, and so on. I show this in my picture.

It's an expensive design (uses lots of transistors), and it's not really useful for small adders.

Thanx ikanayam. Your design saves some transistor at the setup stage

I was thinking if the setup stage and the Carry logic has something to do with the Carry Look Ahead algorithm.

Setup : P = A+B and G = A.B

Carry Propagate : Cout = P.Cin + G

btw, I need to test on the Carry Select Adder and see how many transistor and the critical path taken for an 8-bit setup, and also if it is bulky when expands to 32-bit in the future. My current design is using two 4-bit CLA link together with ripple carry, i'm afraid when expand it to 32-bit it will be quite slow and bulky.

Here's my CLA + RCA design. The MUX is placed at the input port to select 1 of the 3 sources using the adder (register, multiplier and divider). DEMUX is placed at the output port to do the same function.




Attached thumbnail(s)

why do you have demuxes at the ouput? looks redundant to me. I'm not sure how your design is supposed to be, but can't you just wire the outputs to whichever circuit you want them as inputs?

Yup, you are correct, DEMUX looks redundant.

Last time i don't have the 'EN' line for other functional units such as multiplier and divider, so hv to use DEMUX to choose the output. This semester i suppose to minimize the gates and critical path, at the same time remains some good speed.

Sigh.. 1st time doing this kinda thing, many problems here and there. I'm sure you are expert liao fishchicken


* Who's studying electronic engineering course pls report in here.
We can help each other in any difficulties in engineering

AFAIK, only a few are taking this course :
ikanayam, silkworm, empire23, winc87, charge-n-go....

Who else, mari mari lapor diri

This post has been edited by charge-n-go: Oct 12 2005, 06:46 PM

silky is a veteran already... no more taking courses like us n00bs heh.

Btw your multiplier and divider are utilizing the same adder circuit using shift and add/subtract? Or they are completely separate circuits?

Ohh.. really? He's now working or taking master degree? Maybe taking PhD liao, hahaha.

Ya, my multiplier and divider is using the same Adder/Subtractor with some shifting logic.

btw, how's yr ALU going on fishy?

Well, this is the datapath i designed last semester with another team mate.


Attached thumbnail(s)

i took computer engineering...about 7 years back...since then, i never use the knowledge in my work life...my work more towards marketing and business...hehe...u r saying u guys are noob...i think i'm noober than u guys r...
sorry for posting non relevant post...

This post has been edited by remysix: Oct 12 2005, 07:35 PM

icic, nvm. Pls advice us if anything we do is wrong. Added you into the list

who know how to use Silvaco here?

BEM #46370R
branch ELECTRONIC

EE student, but more into digital systems and VHDL/Verilog programming

anyways charge-n-go, i suggest adding registers on the input and output if you're gonna implement this on a real board(or FPGA for the matter) unless this is just a theoratical(gate level + simulation) assignment and nothing more

p/s: anyone heard of Viterbi decoder or Convolutional Coding Encoder? got tough time understanding it...

This post has been edited by X10A Freedom: Oct 12 2005, 09:47 PM

Computer system engineering here. I studied the adder, digital logics stuff u guys were talking about last semester. but now forgotten everything. haha.. gotta search for the notes to refresh everything.

btw, anyone familiars with discreet signal processing?

This post has been edited by nerd nation: Oct 12 2005, 10:28 PM

UM Electrical Engineering Undergrad here.
Count or not

This post has been edited by Tingwc84: Oct 12 2005, 11:56 PM

Hmm, electronic engineering first year 2nd semester. Lecturers have juz started teaching digital logic gates.

mmu gamma year EnE.....but i know nothing,except V=IR

Hm... you can integrate your shifting logic into one of the input registers directly if you don't need a barrel shifter. You just have to loop back the connection into a mux and skew the bits left or right by 1. If you need to shift, just select the mux input with the skewed bits. Need 2 shifts? Clock it twice. Of course if single cycle shift performance is important thing then you need a barrel shifter.

Another idea is that you can make the outputs to your multiplier/divider 8 bits wide externally. That way you can make your large mux only 8 bits wide and save a lot of logic there. The key is to output the results in 2 clocks.

silkworm is working, not studying anymore. that was the last time i checked anyway heh.

Ok i got a question, anyone know if it is possible use/modify an adder/subtractor unit to do AND and OR operations on the inputs? I'm talking about a minimal alteration. Trying to get rid of the mux on the output...

Have fun with propogation delay... looks like the cct can run about 200MHz at most..

nothing to add here cause i'm late for work..