i am computer repairer and service for my friend and family!

The most hardest hardware to build apa?

i think CPU lah!

Sorry, my bad, I should have noticed the context

I see your point, but correct me if I'm wrong, besides IP design the rest of the job becomes much simpler if PLDs (especially FPGAs) are used right? I think that's good enough for Malaysian companies to contribute to strategic niche industries, and anyway FPGA growth atm is outpacing ASIC growth, according to

I have some much better thought out ideas on this but i'm not so sure i want to put valuable IP on a public forum...

... there's one more area where FPGA are used out of necessity: low volume systems. I've used production quality 4-socket ISDN line cards (meant for ISDN routers) that were powered by Xilinx FPGAs.

And no, I don't work for an FPGA vendor

edit: removed. i just realized that some of this stuff might be confidential. don't want some company stealing my idea lol. if you already got it, please stfu ok

No , I don't work for Altera. I am a customer of Altera and Xilinx so every month they will visit me and ask me how many more FPGAs i would be using in such and such project .

should have put this earlier , sorry , forwarding this.

Altera and xilinx are more or less equal. In every mature industry , you usually get duopoly , like in the CPU world , AMD vs Intel , and in the GPU work , Nvidia vs ATI. Seriously they try to copy each other specs , so i don't find arguing abt which chip or company is better any interesting at all.

We get support from s'pore. Even though Altera is in penang , but those are what they call the "factory" guys. They don't go out and see customers at all. Unfortunately, malaysia is still not a very big market for FPGA, so a lot of support we still have to get from s'pore.

There's still a role to play for ASIC chip but FPGA has gain a little bit more market recently as the price has come down significantly. I am mainly doing acquistion , digital triggering, filtering and stuff. If we use ASIC chips , we have to have a huge team for ASIC only and takes so long to verify it. FPGA is the fattest way of doing things, only concentrate on the design and algorithm , don't even need to think of 0.18, 0.13 , 90 nanometer and yield. xilinx/altera has to sell us chips that 100% work , or not we will go after them

why do you wanna get upset with that ? Do you think sales engineer are really engineers ? It's just a name, just be happy with what you know, not what people are addressing you as .

ASIC is way out of my league, my hobby is to program MicroC from Microchip. Now I'm working on Radio Network Servers.

For FPGA, I did a bit of VHDL during Logic lectures hahahahha

Usually I use 16F877A for PWM and ADC. If those are not required, then I'll go for 16F84A. Haven't tried 18F though

design support. let say we use some of their IPs like some DDR2 memory interface(it's too commom nowadays , don't wanna waste time designing it) , we might come into problems integrating into our design. Or maybe we need to understand if the change the pin constraint specify by the vendor , how would it impact timing ?

Most of the time we don't care much about the rams , the async FIFOs , adders and so on has we already have so many proprietary blocks that we need to design. So with their design support , we can get more help if we come across problems from things that are not designed by us.

It depends on the input clock also. For example, the input clock is 20Mhz. A PWM 8-bit registry specifies the percentage of the input clock to the PWM generated. If you put 00000000 to the registry, means the PWM will be 0Hz, if you put 11111111 to the registry, the PWM will be 20Mhz, if you put 10000000, the PWM will be 128/255*20MHz. Hope that you get what I mean.