welcome [ r u g a ].
ERmm.. anyone knows how to extract certain bit from 'add' function?

Let's say,

SIGNAL a,b : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL reg : STD_LOGIC_VECTOR (7 DOWNTO 0);

reg <= (a + b) from 15 downto 8.

What i mean is i need info from the added result A+B (bit 8 to bit 15) into reg. How can I actually do it in 1 clock only?

Thanx

reg must in 8 bit by definition? highlighted is not the actual syntax right? no "from 15 downto 8" right?

can i know in 1 clock means that must in 1 instruction line only?

sorry, too long din do vhdl oledi..

is it possible to shift a and b bits 1st before adding?

add another signal
RESULT : STD_LOGIC_VECTOR (15 DOWNTO 0);

reg <= result[15..8];
i think should be written this way
or else it will be
reg <= result[15 downto 8];

reg must in 8 bit by definition? highlighted is not the actual syntax right? no "from 15 downto 8" right?
can i know in 1 clock means that must in 1 instruction line only?
sorry, too long din do vhdl oledi..
is it possible to shift a and b bits 1st before adding?

I've tried this actually:

add_result <= A+B;
reg <= add_result( 15 downto 8);

But using this method, A+B will be stored in add_result upon clock, and the previous clock add_result will be input into reg.

ok, then update 'reg' outside of the clk event(after the end process statement)
it should save u 1 clk cycle

but how do we update the reg outside clock?
add_result will be sent directly to bus, thus tap bit 15-8 to reg?

Load A , Load B
A+B <- clock cycle
add_result <= A+B
reg <= add_result( 15 downto 8) <- clock cycle

1 cycle for A+B
1 cycle for store add_result to register

im rusty in this =___=
but how do we update the reg outside clock?
add_result will be sent directly to bus, thus tap bit 15-8 to reg?
oh well, reporting in

i tried b4, but the result isnt correct.

THis is actually my code description:


Anyway, welcome e-jump

I dont think can update if there is no clock

afaik, registers dont need clock to update
we can assign bit load and bit clear

bit load enable = load reg content to bus
bit clear enable = clear content

amirite?

afaik, registers dont need clock to update
we can assign bit load and bit clear

its the same as clk
clk is just train of pulses and the register updates at every pulse
normally when we refer to update according to clk, we meant that the registers are edge triggerred circuits

wierd.....it should work since

add_result <= A+B;

so by just putting this code

reg <= add_result( 15 downto 8);

at outside of the process statement will meant that you are tapping the 15 downto 8 bus to 'reg'

Yes you can do that.
You mean a synchronous circuit? they can be still edge triggered asynchronously like above

no, i meant registers in general
there aren't any registers that consist of latch though(dun count in pulsed latch) which are level sensitive circuits

Okay...

I need you guys opinion here.
" IS THERE SUCH THING AS NEGATIVE RESISTENSE?"

Since high school and 4 years in University, the basic thing I learned about resistence is that there is NO MATERIAL in this world that can give -ve resistence i.e you get -ve ohm in multimeter.

If you get such reading in first place, it is either that you have not calibrated your multimeter or the multimeter is faulty...
But in technical explaination, if you get -ve reading it means that the material you are testing is GIVING OUT energy, i.e generating its own energy, and Im not referring to dry cells or any other type of batteries.

A friend of mine was taking a reading of a wire (basically a grounding wire), and he got -ve reading. When I told him that his reading was wrong, he said that the reading is correct and it read -ve because the material is very good. The reading although only read -0.4ohm, it still makes a lot of difference in my line of job.

So I need you guys professional opinion whether the reading taken by my friend is correct and Im wrong or vice versa?
Note that this is not to prove who is right or wrong, but it is important that an accurate reading is taken due to the nature of job...

how about do like this? having two process?

Hey since I dont get any response in Education forum... can someone enlighten me on this

My fren tried, but not really working
nvm, i'll try another method.

thx everybody for helping.
i only learnt about 0 resistance, which happens to superconductor at very very low temperature. -ve resistance? i need somebody to enlighten me too