studying at kbu, the butterfly section is not done by me
it's using mentor graphics ic flow, i use my school's pc to capture the screen as such tools aren't available as freely as Altera products

oh.. KBU got mentor graphic, but MMU doesnt have ler
I tried to find lanun in LYP, found nothing. hahaha.

btw, do u got any jobs after graduation?

dun bother searching for lanun especially in LYP, it's pretty futile
u can try the great intr@n3t though
if u do find one, care to share with me too XD
jobs after graduation......hmm, that's something i'm hoping for but things aren't going to smoothly though
already missed one interview from altera
but they might be coming back, so keeping my fingers cross
anyways, anyone here have any knowledge on mentor graphics boardstation(aka EN2004 which includes Accusim, Design Architect etc) tools? i need to verify something about that especially things regarding LVS

This post has been edited by X10A Freedom: Apr 3 2006, 08:51 PM

EDA softwares uses license servers (just google FlexLM),so i doubt you can get a lanun version to work properly. (if you can tell me... 1 annual license for a simulator = 6 engineer + 1 supervisor's pay)

Sorry I don't do LVS, can't help you here, but basically what they do is match the layout to the schematic right? Should be pretty much straight forward.

Altera is hiring quite aggressively right now, my guess is they are expanding their design centre in penang. If you do get hired by altera, congrats.. they are one of the highest paying company in Malaysia for fresh grads at the current moment. The other one that comes close is Shell

well, i need to know how to setup the Design Architect so that i can do LVS with the mask layout
i need to confirm that my college is lacking of something that stops me from doing this

seems like u guyz only interest in digital and vlsi design.

other specialist here, any?

ahah, it's called the computer engineering thread, sure more on digital stuff la

wanna talk about digital signal processing? DFT and FFT anyone?

X10A Freedom: Altera questions arent that hard. If u hv done layouting b4, it should b easy for u. I've tried and confident but end up not called for interview, js bcoz I'm not 1st class student

i used to like DFT and FFT when in college but since now hardly can use these kind of skill..so forget oledi..lolz

now my skill is more towards embedded system and power related design..lolz

yah, Altera interview questions are quite easy for fresh grad but not me, coz forget many things oledi ... but beware they will trick u..lolz

well, when i was attempting the questions, i haven't really learn layouts in detail yet(they only gave me like few days just to prepare )
after they processed the answers for the questions(which took quite long), i've mostly done on my layout, but too bad, i wasn't call up for the interview(though some of my classmates did but only 2-3 person in total was really confirmed after the interview)
but my lect was telling me that the ic design department might want to go for a 2nd round recruitment.......so i'm hoping that this time, i'm well prepare for it

get to hear from my interviewver about ic design group. lol

i'm applying application engineer

hmm... where r u working now ar?
well, my answer is same as my fren (we sit side by side n compare la), but he was called not me, moreover we apply for the same job position
so i suspect is my CGPA ler, he is way higher than me


U mean ASIC? AFAIK, they only want experience engineer or fresh grad in this kinda field, maybe u can la since u did layouting

Japanese MNC, last time very famous the name but after merge with some other Jap MNC, then i guess u will never heard it before..lol

Altera do filter out the applicant based on CGPA...sad..

hey guys can i join here?
i'm taking CE at UTAR..i'm just wondering does UTAR have the capability to conduct their IT courses well..

i heard that KBU has the best IT courses offered..isit?

wat year? my 2 previous lecturers from TARC had transfer to UTAR..

em i think shud be next year..coz this year i have to take a Foundation course on science stream..

can anyone tell me more about computer engineering..isit a good choice? when i tell others i'm taking IT..they will give comment like canot find job la..very hard to work la or what so ever..

what does this course cover us? if from my reading on the info given by utar,is about hardware design as major..and minor software programing/design..
means we can make next gen. of mobo/graphic card/proc or whatsoever regarding pc right? anyone can correct me?

huh, u choose oledi but regret?

both course have their own advantages, for IT, if u are not good in programming, u will die..even u are good in study is not enuf, u must know various of programming language and if possible learn AI. For the FYP, do somethings grand like AI. For eg my fren, his CGPA is not good but his FYP is good, so his lecturer recommend him to intel and his salary now even higher than me

but some of my IT frens that "study to score" only, will not get good job and pay..they will starting off low pay.

CE is more on analogue and digital circuit design. U will study microprocessor, microcontroller and embedded system as well...for progamming, it will be focus more on low level programming such as assembly language or HDL.

U still will learn C but not those GUI and scripting thingy.

haha..not to say regret..just not enuf info for the course..pros cons..career..not very sure yet..
but one thing i sure is..i'm interested on this course . CGPA is what , FYP ?
ic ic..thanks for the info worh..but i'm still kinda blur on those kind of stuff..not really know anything about it at all..or to say..i'm a total noob on this..
no basic yet

This post has been edited by [ r u g a ]: Apr 4 2006, 01:36 AM

welcome [ r u g a ].


ERmm.. anyone knows how to extract certain bit from 'add' function?

Let's say,

SIGNAL a,b : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL reg : STD_LOGIC_VECTOR (7 DOWNTO 0);

reg <= (a + b) from 15 downto 8.

What i mean is i need info from the added result A+B (bit 8 to bit 15) into reg. How can I actually do it in 1 clock only?

Thanx

This post has been edited by charge-n-go: Apr 4 2006, 05:01 PM

add another signal
RESULT : STD_LOGIC_VECTOR (15 DOWNTO 0);

reg <= result[15..8];


i think should be written this way
or else it will be
reg <= result[15 downto 8];