you know the mask costs close to 100K, and each wafer several thousands... (need to check with the fabs...) anyway, there are only a few fabs in Malaysia, Jabil has one, (not sure which process though), and infineon (me thinks it's 130nm or 90nm).. hell will probably freeze over before intel builds a 45nm fab here....

If you don't need a whole lot of accuracy or linearity, then why not DIY? 5-bits is pretty do-able with an R-2R ladder.

Alternatively, a good ol' 8-pin PIC with 6 IO pins, 5-pins for your parallel input and one pin for the output, just nice! It's extremely easy to knock together a bit-banged PWM output, then just low-pass filter the output pin and you have your analog output.

Finally in the "overkill" department, a FPGA could do the job. FPGAs outputs usually have about 3-bits of programmable drive. Chain together 4 pins (I think) to get your full range of outputs. This solution sucks a lot of power though.

some mask layout images from my final year project, i know it sux , so just bear with it


ever seen a butterfly mask layout?


the whole viterbi decoder:


This post has been edited by X10A Freedom: Mar 31 2006, 07:24 PM

^ LOL whomever did that butterfly part must have been very artsy or very lazy XD

i think he's just purely lazy(with a little artsy)
it could have been more compact if the components on the right hand side were as compact as the left hand side

INTI E&E diploma grad
current Nottingham 2nd year electronic engineering student
reporting in =)

i feel so noob la.. haiz

Haha.. his routing is a little long though... and if he was working his manager would have been a little unhappy with all the blank spaces.. 1 sq milimeter = several millions

Today js changed my 8-bit adder's VHDL from structural coding to behavioral coding. It is Sooooo much faster with behavioral and save a lot of troubles portmapping

Well, behavioral is just 2.4ns (including the buffer register at the adder output), but the structural circuit without the buffer register already have 8.1ns delay and a lot of glitches.

yah, structural modelling is crap...

behavioral modelling is much mroe easier...u use Generic to do?

For a critical circuit (like an adder, ALU, etc) it's always better to hand tune it at gate/transistor level. Synthesizers don't generate optimal speed and size. Problem is his tuning was something you would do for an ASIC, while he was using a compiler for a FPGA, so it's not optimal which is why i think you see the difference.

This post has been edited by ikanayam: Apr 3 2006, 09:56 AM

I use structural in the 1st place to generate my custom adder, well of course it screwed up bcoz the CPLD might not have some predefined LUT or Cell for tat purpose. Fishy i still like the ASIC leh, kinda cool to have everything start from scratch and slowly fine tune. Argghh... still angry y my uni doesnt have the Cadence tool

I'm using Altera MaxPlus 2 with Max7000B CPLD

This post has been edited by charge-n-go: Apr 3 2006, 10:25 AM

Maybe you can look into optimization for that kind of logic, optimization is always fun and it's good experience.

I've tried various methods, behavioral still the best

Human optimization lost to compiler optimization, damnit

Left 14 days before report submission for my CPU. I hate documentation !!

Documentation is something that engineer hate but cannot avoid..lol

like now i suffer doin my report for my project...i also lazy to do but if not, my boss would kill me

btw, i use Xilinx Spartan XC3000 last time...old FPGA

I'm simulating with Maxplus 2, but final implementation will be in Spartan 3 Starter Kit CPLD. Still waiting for its arrival

I'm not sure if the VHDL code can be transferred to Xilinx successfully. THeoretically its possible la, but still scared ler

defintely can since HDLs are meant to be portable to any platform that supports it
but expect the result to be different from wat u did on MaxPlus2
it maybe faster, or slower

How about what the compiler considers synthesizable? I'm sure there is a difference across different compilers. That's the only potential problem i see.

This post has been edited by ikanayam: Apr 3 2006, 03:05 PM

normally the codes are synthesizable no matter what, it's just that the result of the synthesis may be different(gonna be bigger in size or so? depends)
therefore people use 3rd party software to do simulation and synthesis(mentor, synopsis etc) so that the end result doesn't varies for different cpld/fpga

p/s: aren't u supposed to be sleeping too much coffee or so? XD

This post has been edited by X10A Freedom: Apr 3 2006, 03:40 PM

Well speaking from personal experience, previously i've made the mistake of writing code which can be simulated but cannot be synthesized. And not only that, different synthesizers are picky about different things, one of them may let you use packed wires while another will not etc etc. Just one of those little annoying things which were never emphasized from the start, which i think is a huge mistake when teaching ppl verilog. I'm sure it's the same with VHDL.

Going to sleep soon, just finished another layout so i'll sleep now

This post has been edited by ikanayam: Apr 3 2006, 03:46 PM

Tat's what I'm afraid of. It may work flawlessly and fast enough in Max7000B, but when it is synthesize in Spartan 3, maybe got minor glitches during the positive clock edge, then die liao

Well, js pray i can successfully transfer it, if not presentation time will kena from moderator

btw X10A Freedom, where r u studying? May i know where u got the tools to construct yr butterfly layout?