Load A , Load B
A+B <- clock cycle
add_result <= A+B
reg <= add_result( 15 downto 8) <- clock cycle

1 cycle for A+B
1 cycle for store add_result to register

im rusty in this =___=
but how do we update the reg outside clock?
add_result will be sent directly to bus, thus tap bit 15-8 to reg?


oh well, reporting in

This post has been edited by e-jump: Apr 4 2006, 08:43 PM

afaik, registers dont need clock to update
we can assign bit load and bit clear

bit load enable = load reg content to bus
bit clear enable = clear content

amirite?