Official offwork time is early, but the work always have to finish beyond working hours. You want meh?

Hey, are u doing layout design there?
Actually for big company like Intel and AMD, they still can bear the cost of masks.

See how many steppings they produced? K8 alone has up to G step, and Core 2 already goes into G step now. Merom on Santa Rossa platform will be on E stepping (E1 in specific), imagine how many masks Intel is using

nah, not layout design
but we have to know a bit
my company dun like to produce so many masks
they prefer to produce mature masks(that will be after so many revisions in the foundry )
and also ur company have their own fabs so it's easier to control

So what r u doing currently?
* how i wish that's "my" company, hahahha

clock networking
damn headache for the past few days

the clock tree ????? he he he he
use FPGAs. They have global clock nets and regional clock nets with minimum skew. I never need to think about them anymore. What's more, they have DCM and PLL inside the FPGA that allows me to deskew , re-synthesize the clock and so on. Wonderful stuff.

Haha yeah. Super important stuff which n00bs always ignore forget to plan for in their designs when doing ASIC projects. I had quite a bit of fixing to do last semester because my teammates completely ignored the issue, and i forgot to tell them earlier.

This post has been edited by ikanayam: Nov 22 2006, 09:27 AM

Oh well, i think Freedom's job scope is not suppose to use FPGA to replace clock network

haha, we're using networks similar to FPGA

lmao, i'm not headache doing the muxes and networks
but more into the proper definitions of it (some ppl just won't want to change their damn flow )

ah, to a certain extend, there are some similarity
but if use FPGA's network to replace the current one, it'll be damn mind boggling to shrink the die size(FPGA have too much redundancy)

This post has been edited by X10A Freedom: Nov 22 2006, 10:39 AM

So you are a structure ASIC design engineer ?

for the moment, yes

some PWM controller can control the On and Off rather than it has to be equal, for example:-
_ _
_| |_| |_ equal
__ __
_| |__| |_ equal
_____ ____
_| |_| |_ not equal

it cant be shown properly after posting, to put it in words, some can control the length of 5V and 0V rather than making it the same.

<http://www.eetasia.com/ART_8800438019_480100_d511c27a200610_no.HTM?dmsource=EETAOL_061122_EETAOL>
some interesting facts about design trends in Asia Pacific

hmm..ic. So more bits will have a more precise output right? Usually the clock speed for PIC is within <50MHz range?

Anybody likes to discuss GPU architecture here? I'm particularly interested in DX10 and Unified Shader

The scope is massive. What about them do you want to discuss? Btw Dx10 does not require shaders to be unified in hardware, although it does make sense to do it.

Hmm... maybe the latest G80 and the Xbox 360 graphic engine? I think opening a new thread in HW is pretty useless bcoz not many of them are interested also

So far I only read xbitlab's article on G80 architecture. cant fully understand thou

beyond3d has a good article. what do you want to know exactly? there's a billion things that can be discussed, potentially.

Just some normal discussion on that. No specific area. We just share whatever we know

well, maybe u can start off with DSP architecture and slowly branch towards graphics engine
i'm sure fishchicken has lotsa articles on it