hmmm , some interesting topic here. Can i join the family ?

I was previously a ASIC front end designer, only doing RTL design and some simple synthesis job. Most of the time only writing VHDL/Verilog RTL. Now switch to full time FPGA design and abandon ASIC. FPGA has more system level design compare to ASIC.

Hi charge-n-go ,

I work in one of the MNC in penang, mostly in instrument design

We have instrument that use 3-4 FPGAs but cost is not a problem as we got higher margin. FPGA design and ASIC design is more or less the same on the front end , as in RTL design part. We still have to code all the design in VHDL or Verilog. But obviously they are block rams , embedded high speed 500mhz multipliers , special adders blocks that we don't have to code. We treat those as black box and use it to make a more complicated design. For example , if you want to design a FIR filter with a lot of taps , you don't care much about the MAC(multiply accumulate) , you just care more about how to do it and the algorithm.

This post has been edited by lgh: Nov 21 2006, 05:18 PM

No , I don't work for Altera. I am a customer of Altera and Xilinx so every month they will visit me and ask me how many more FPGAs i would be using in such and such project .

should have put this earlier , sorry , forwarding this.

Altera and xilinx are more or less equal. In every mature industry , you usually get duopoly , like in the CPU world , AMD vs Intel , and in the GPU work , Nvidia vs ATI. Seriously they try to copy each other specs , so i don't find arguing abt which chip or company is better any interesting at all.

We get support from s'pore. Even though Altera is in penang , but those are what they call the "factory" guys. They don't go out and see customers at all. Unfortunately, malaysia is still not a very big market for FPGA, so a lot of support we still have to get from s'pore.

There's still a role to play for ASIC chip but FPGA has gain a little bit more market recently as the price has come down significantly. I am mainly doing acquistion , digital triggering, filtering and stuff. If we use ASIC chips , we have to have a huge team for ASIC only and takes so long to verify it. FPGA is the fattest way of doing things, only concentrate on the design and algorithm , don't even need to think of 0.18, 0.13 , 90 nanometer and yield. xilinx/altera has to sell us chips that 100% work , or not we will go after them

why do you wanna get upset with that ? Do you think sales engineer are really engineers ? It's just a name, just be happy with what you know, not what people are addressing you as .

These are so called PIC microcontrollers rite ? I used to learn how to program these chips in the Uni long time ago by writing chip instruction specific assembly code. fun stuff.

Now dealing with a lot of 32 bit processors like powerpc , ARM. As microblaze(xilinx) and NIOS(altera) seems to be getting more and more acceptable in the market , there's a plan to actually put all these softcore processors into the FPGA !!!! more work !

The good thing abt softcore processor is that it's just so flexible. i can hook up anything i want thru the peripheral bus. i can even include or exclude a simple FPU.

design support. let say we use some of their IPs like some DDR2 memory interface(it's too commom nowadays , don't wanna waste time designing it) , we might come into problems integrating into our design. Or maybe we need to understand if the change the pin constraint specify by the vendor , how would it impact timing ?

Most of the time we don't care much about the rams , the async FIFOs , adders and so on has we already have so many proprietary blocks that we need to design. So with their design support , we can get more help if we come across problems from things that are not designed by us.

Ok, as you know for altera support , you have to go thru achieva components , and for xilinx , you go thru avnet. They are more distributors in asia pacific and i am not going to name everyone , so sorry about that. So we asked altera/xilinx for design support , everytime we still have to go to the s'pore site. penang might be the regional support center , but we still have to go to distributors.

the clock tree ????? he he he he
use FPGAs. They have global clock nets and regional clock nets with minimum skew. I never need to think about them anymore. What's more, they have DCM and PLL inside the FPGA that allows me to deskew , re-synthesize the clock and so on. Wonderful stuff.

So you are a structure ASIC design engineer ?

<http://www.eetasia.com/ART_8800438019_480100_d511c27a200610_no.HTM?dmsource=EETAOL_061122_EETAOL>
some interesting facts about design trends in Asia Pacific

talking abt DSP , I find it alarming to come across so many candidates that have no clue on Nyquist sampling rule. That is like the most fundamental theory before we even go into signal processing and stuff. some can't even answer what would happen if you feed in signal into an ADC that violates that rule ( answer : aliasing ).

What thing ? DSP ?