Here the link.
Links

-pWs-

same

Aiyaa...
Go to the site click on Hardware News will do.

-pWs-

There is a Phenom "Black Edition" huh. Didn't know about this though.



Source : http://www.xbitlabs.com/articles/cpu/displ...m9600-be_2.html

We saw that quite some time ago.. just didn't want to comment much of it, basically the outcome was still the same as other Phenom (non Black Edition) reviews.

Anyway, just for your information.... try looking up on Google (or other search engines) on this...

"A clock interrupt was not received on a secondary processor within an allocated time"

Seems that some batches (quite a number, really) of Phenom shipped came with a defective or much slower 3rd core. This caused BSODs even on stock clocks, and its NOT related to the TLB bug... Possibly now we are beginning to see the reason for AMD's upcoming Triple Core... So anyone with Phenoms encountering this problem, suggest or recommend RMA that processor...

This post has been edited by lex: Feb 21 2008, 10:48 AM

How to check/know if the phenom have a 3rd slower core? I do not experience any BSOD on vista32bit.

This post has been edited by lex: Feb 21 2008, 11:00 AM

Wow...
I like black colour...
It looks nice...

But it seems it isn't quad core....

If no BSOD then it should be OK, possibly not the defective batch... However, to test it, try stressing all 4 cores at once (most of the time only 2 cores used on most programs)..

More info here...

http://www.xtremesystems.org/forums/showthread.php?t=175878
http://forums.amd.com/forum/messageview.cf...d=y&STARTPAGE=1
http://www.tomshardware.com/forum/248265-2...ing-flaky-cores

... the rest search on Google...

Wow..Didn't know about this problem with the Phenom though. Yea, you are right regarding the performance. From the charts shown in the review, it really shows the BE aint significantly better than the non-BE. Nothing much to shout about as well..

So, in this case, what do the people who have defective batch do? RMA?

It started since Phenom became available. They thought it was the TLB issue, but even after the patch was applied, the problem continued. Then some of the owners noticed the actual source of the problem during testing... rest is history.

As can be seen from those links, RMA was the best choice and they got back a full working quad core.... UNLESS you want to continue using a "triple core"?

Haha...First Tri-Core available Anyway, its definitely not a good thing to AMD as i doubt anyone would want to buy something that they know, there is a high chance of RMA even though its brand new.

Deneb 0MB L3

xcept for the unlock multiplier...what else the black edition can do...i mean izzit any better than the ordinary Phenom..

GTG

0MB L3 cache?even the L2 cache is damn small

i gues the 0MB L3 cache just for value proc and the 6MB L3 proc for performance proc

just my opinion...

AMD finally ships B3?

Deneb, Propus and Heka...

weird code names will appear end of this year

Deneb should be cheap.
I mean really cheap.

Really.
Cheap.

It's definitely <200mm^2, and while ikanayam disagrees with me on this, I suspect its diesize could be 150-70mm^2 (depends on how many HTT pads left)

150mm^2 is quite small. It's *half* a 65nm Phenom.

For games and threads that run discrete (no shared data) it should be faster than current Phenoms (due to IPC increase) and for reviews showing games, that's probably all that matters.

If the L3 is the obstacle to the Phenom going to higher clocks, they might get a wall broken here too. No more added latency, I might add, should also help some...

http://chip-architect.com/news/Shanghai_Nehalem.jpg
With 6MB L3, it's going to be around 240mm^2, about the same size as the nehalem. With a 2MB L3 (which is very likely going to be available, looking at the L3 layout), it's going to be around 180mm^2. The 2MB version might have 2 less HTT pads, but that doesn't save much. I don't think there will be 0MB L3 versions because it seems like the L3 is probably an essential part of the memory heirarchy.

The L3 isn't really an issue for clocks. It runs at the memory controller clock, which is much slower than the core clock.

This post has been edited by ikanayam: Mar 16 2008, 10:08 AM

Well for one, looks like L3 sapped a lot of power and produced hotspots (not the wifi kind) on Barcey. I do think that it's partly responsible for the 230Mhz HTT wall considering the NB clock, IIRC scales too (the black edition chips were duds in their own right, some people reported OCs much lower than the stock 9600s even w/o the HTT wall limiting them)

K8x2 didn't have L3 and it was pretty good. You'd have to reconfigure the fetches, but I'm not sure L3 really did help Barcelona besides better-than-usual crosscore scaling, which HT is also part of helping.


L3 shouldn't have been reintroduced. It brought AMD most of their 07 CPU problems IMHO.

It is extremely unlikely for cache to cause hotspots unless there's a huge problem with the cache design. In which case you probably wouldn't put such a flawed design into production. I think the NB/L3 clocks will have a max speed per cpu generation, they won't directly track core clock increases.

As you have more cores, a unified lower level cache makes sense if the coherence controller is smart enough to use it for data sync between cores. Else all this traffic has to go through memory, which is way way slower. It's not the L3 that's causing them problems. They're having issues with caches in general.