No, not really. They never won much until they had decent performance with the K7 and K8.

And that's a big IF since we don't really know the real world crunching numbers and latency of Nehalem since if Intel gets it right (I'm not the betting person, but if I did, I wouldn't bet against it) we're going to see another major leap forward. As it is with Conroe/Penryn still utilising traditional NB mem controller interface to do the work and yet negate most if not all integrated mem controller's "real-world" advantages, what more if they successfully implement it and take advanatge of their large cache technology

I can't disagree with you on that but one has to consider the fact what with Intel forging ahead with larger cache at L2 instead of going L3, and at the same time developing tech which negates or reduces the latency associated with large cache, it's hard not to be imginative with what may possibly be achievable once implementation of integration is achieved and if it's inline with what the goals of HTT 2.0 are, we may see greater bandwidth being made available altho by right current microproc designs being churned out by Intel aren't that memory hungry (Correct me if I'm wrong, getting forgetful nowadays). And with that, it's possible a substantial if not leapfrogging evolution of micro-p architecture at consumer market level. As for Northwood, I can't personally agree it's a failure since it did serve it's purpose well eventhough it close to it's design limitation. Prescott and subsequently Cedar Mill should be the one's to be considered the real flops as Intel chose to prolong a design which was fast running into a performance-per-watt wall. IINM, Cedar Mill's heat density scaled to the point that at an equivalent one sqaure meter, it generated enough waste heat equivalent to a small power plant (Thanks to ikanayam for pointing out that fact last time).

As for Bloomfield, from what I heard from the grapevine, that seems to be a stop-gap measure although I can't get nor divulge any further details since it's unsubstantiated and/or it's based on the trust as friends

Quite suprise to see Phenom also loses on the memory benchmark.
Just reinforce my opinion that the Phenom is a failure. 

so... u got any real world performance u wanna show wif ur X2...? i got bad enough exp wif X2 3800+ wif 4x512MB RAM on a MSI nforce 4 ultra chipset... lost to Celeron 430 on Intel 945chipset + 1GB RAM in term of software loading, networking speeds(file sharing and remote monitoring), etc... every real world performance also lost... but i partly blame it on MSI's crappy mobo...

My "hands on" exp as a technician proof tat Intel's core architechture outperformed AMD's X2... i also built PC's for CCTV monitoring systems... and Intel Celeron 430 on Intel 945 chipset is my best choice for best value/performance... and even reliability...

http://chip-architect.com/news/Shanghai_Nehalem.jpg
With 6MB L3, it's going to be around 240mm^2, about the same size as the nehalem. With a 2MB L3 (which is very likely going to be available, looking at the L3 layout), it's going to be around 180mm^2. The 2MB version might have 2 less HTT pads, but that doesn't save much. I don't think there will be 0MB L3 versions because it seems like the L3 is probably an essential part of the memory heirarchy.

The L3 isn't really an issue for clocks. It runs at the memory controller clock, which is much slower than the core clock.

It is extremely unlikely for cache to cause hotspots unless there's a huge problem with the cache design.

You want to isolate just the CPU when finding the max cpu clock. So adjusting multipliers is the best way to do this, to keep memory from affecting the overclock. If you want to go to extremes, a much less extreme intel overclock will easily smack the phenom anyway so it's pointless either way.