No wonder cstkl1 mentioned about Rocket Lake being a very stable platform
https://www.reddit.com/r/intel/comments/mh2..._advantages_of/QUOTE
But this was only the beginning. But until Apex Legends, no game had brought out the multi-score "Skylake threading" problem like this, and even though no one knew anything about this at the time, this "Internal parity error" crash and Apex needing a new code path to bypass the threading conditions was the result of the Skylake interconnect system being stretched to more cores, and helps explain the even bigger latency penalty on CML cores (relative to core position on die).
Minecraft was a java game that had been out for many years now, and at the time, Minecraft crashing was usually just people's windows being corrupted or drivers out of date. Minecraft generating "Internal" errors was completely unheard of at the time. Parity Errors simply didn't occur unnaturally on 4C/8T processors since the architecture hadn't been extended to its breaking point. If you actually got a parity error on 4C/8T, you were truly unstable and were probably waiting for a L0 or a BSOD. Even the 6C/12T gen was mostly overlooked since it was so brief. When the 9900k hit, however, this is when more users started noticing Parity Errors being generated by MC, although no one had a clue what was going on.
What broke the camel's back was the 10C/20T CML.
First, OC'ers noticed that cache/RAM latency went up (as mentioned above). This was obviously forced to happen, but users were rewarded with yeet RAM overclocks from a stronger IMC, and 5.3-5.4 all core overclocks on good chips, which kept CML competitive with AMD's offerings, as AMD simply couldn't touch Intel on memory overclocking. But as thread count went up, the problems causing Parity Errors became more obvious, as players started encountering Minecraft errors in droves, some people even on stock clocks, and some AAA Games (like RDR2) were also generating Internal WHEA errors. The L0 error was already well known; errors on virtualized instruction registers in the L0 register store, which only happened on hyperthreading enabled processors, which was already the major issue with skylake stability. You could push high overclocks and get random L0's which were very difficult to stabilize, depending on the instruction set used, but enough vcore would fix it. But the parity error showing up on systems that passed stress tests was the sign that Skylake, never meant to go up to so many cores, needed to die. And with newer RTX/DLSS games now starting to generate Parity Errors on daily stable systems, something needed to be done.
Enter Rocket Lake.
While Rocket Lake is prep for Intel's true next gen platform, Alder Lake and DDR5, Intel needed to prepare this platform for maturity, while moving on from Skylake and all its bugs. While ADL is rumored to have two IMC's, the backport of Cypress Cove to 14nm, with only one IMC and the Gear changes, hurt RKL considerably. But this is a necessary evil because Skylake HAD to die. And the IPC increases (~19%) are real and will only keep getting better on future gens. But with people breaking NDA, and releasing benchmarks with pre-beta Bioses and broken memory overclocking, showing off terrible bandwidth results (NDA's exist for a REASON, people!), every single person overlooked something.
Stability.
The Death of Skylake also meant the death of Skylake bugs.
CPU Cache L0 errors are now a thing of the past. No more random L0's thinking you're stable and only partially stable with BSOD's that look like RAM errors (System Service Exception, IRQL_NOT_LESS OR_EQUAL, etc). You just BSOD now, with the well known "Clock Watchdog Timeout", or in other words "I'm not stable, chump, try again". There's no more "middle road". You're either stable or you BSOD. (I'm referring to the CPU core itself, NOT to the IMC or RAM errors--those still will happily make your life interesting).
Parity Errors are byebye. No longer will Minecraft generate parity errors due to garbage collection in the caches. Now it just runs. Or you BSOD.
The rules have changed for stress testing.