my fav e&e forum:



all your needs is there

am i allowed to ask some education related questions here?

alrites, thanx for your advice

I think it's bcoz each IC have an array of same gates, so if we mix the gates, we need a few ICs to construct a circuit. Besides, from one of the book i borrowed from library (not with me now), it says the NAND and NOR gate has lower latency compare to AND, OR and XOR. Well, all these is based on IC design, not sure about FPGA thou.

Thanx draggy for the info, and Ash, u can ask the question here as long as it's related to engineering

Its best to use NAND gates because (IIRC) it uses about 3 transistors to design it.. By mixing up all the gates, it makes it harder to manufacture. By having only a single NAND, it is easier to organize the transistor to have optimal routing between the gates. It is easier to make the mask for the cct too..

Another point about only using NAND is the simplification in calculating the propogational delay with in the cct. hence easier to clock it up..

Well, that's new info to me

Anyway, do you know how many transistors in AND, OR, NOT and XOR?
Do u know of any good websites about all these things.?

ah i just remembered... look up sendra and smith - microelectronic circut. NOR and NAND gates has 4 cmos transistor.. AND and OR gates are basically NOR/NAND inverted.

I can't really remember why you would use the NAND gate rather then NOR gate but it has to do with the Pull up and Pull down. Probably ask silky about this.. i haven't touch these stuff for 4 years already... now i deal solely on with microsoft products..

Here's a website about logic gates. Hope it helps.
http://www.allaboutcircuits.com/vol_4/chpt_3/index.html

sweet, i didn't know there's such forum

if i recall correctly, FPGA are kinda different, coz they're using programmable array to do the job and normally they mix OR and AND gates
if you want to learn more about the internal structures of FPGA, Xilinx Foundation series would be the best way to learn it(since it's layout editor shows you the FPGA internal contructions)
but i think your uni should be under Altera University program, so using a Xilinx would be quite out of the question(unless your uni still have some Xilinx board)

actually don't bother about learning all these first coz i'm sure u gonna learn it in your final year
but if you're really interested, you should take a look at books that are into IC design , they are really good coz they teach you how to change a Boolean expression from gate level to transistor level then to mask level
the basic idea is that it always consist of pull-up network(p-type transistor) and pull-down network(n-type transistor)

Thanx nutz, winc87 and X10 Freedom.


Sadly, I'm in final year and already taken all the computer subjects (i take it earlier than schedule and push the maths based subj to the final year). My uni (MMU) kinda stupid ler, never teach all these to computer majoring student. I don't even know what is PMOS NMOS circuit like. All i studied is digital logic design and digital computer design for discreet electronics. (all gate level only, and hv to learn VHDL myself). I wonder why i need to take subjects like Analag Comm, Digital Comm (using fourier analysis), electric power system, electrical machine and stuff like that.

Well, i proposed '8-bit CPU' as my final year project title. Already have the basic design except control unit. Now i need to refine and upgrade anything possible 1st before finalize the control unit design. Sigh... it's a tough job.

Anyway, thanx for yr kind advice

This post has been edited by charge-n-go: Oct 13 2005, 09:00 PM

I have another question about the gates.

May i know isit possible to have 5 input per gate? I'm afraid of fan-in problem, bcoz from the book "Princilples of Digital Design' by Daniel Gajski, i see the max of 4 input gates only, don't have 5 input one.

btw, I'm gonna simulate using Altera MaxPlus II, dunno if it support FPGA or not. Sorry for the noob question bcoz I m self learning VHDL and simulator and kinda blur now. Thanx !

i will take degree in comunication and data tranfer computer eng..!

so izzit good? job?

This post has been edited by Mr_47: Oct 13 2005, 11:55 PM

if you want to put in 5 gates also can.. not a problem.. but depending on what method you are using.. TTL? GTL?

EE final student here, currently studying SILVACO software RM200,000. Anyone know SILVACO here? lets discuss about it. I have a couple Q to ask.

If you asking me this Q, I would like suggest you to take Electronic major. This is because it is wide range in EE where students who take it can jump into many EE fields in jobs opportunity. While Com student cannot jump into electronic field or others EE major field, it can but difficult for you later on.

There are tonnes of jobs in Malaysia for EE fields are in Electronic Major.

i think how many input doesn't really matter.......not too sure about that

MaxPlus 2 does support FPGA, but not all
your uni should be using the flex10k chip on the UP2 board right? if it's that then no problem
if you're using Stratix 2, u might need Quartus 2
actually if you're modelling your circuit in MaxPlus2, u don't have to worry about those fan-in problem
the only problem you have to worry is your coding style
at certain times, different coding style might give you certain delays.......

of course, if you want to be slightly lazy, u can try use HDL Designer(Mentor Graphics software) to create the block structure first, then use it to convert into Verilog or VHDL, save some time to write those redundant port maps and entities
XD

erm... actually i mean 5 input per gate

Nope, sorry I've no idea on that. I only know a bit of MaxPlus II


Hmm... thanx for the tips

btw, can i count the delay using conventional way? For example, 2 leg NAND gate has 4ns delay (from the same book mentioned above) and 2 leg AND gate has 6ns. So in FPGA, do the gates having the same delay regardless of the type?

Well, actually i'm using hand drawn (using corel draw actually) to draw out all the gate circuit design, then I'll write the VHDL (using architecture behaviour) in MaxPlus 2. Isit the same as what u meant using the Mentor graphic?
What kind of coding style is more efficient? Behavorial or architecture?


Edit : I have another doubts
If wanna save power when any of the functional unit is idle, can i js use clock gating? Any other implementation besides that? Thanx

This post has been edited by charge-n-go: Oct 14 2005, 01:06 AM

SILVACO question if anyone know

what is the use of term

ATHENA> relax y.min=.2 x.min=0.2

what is the relax actually mean? is it ok if I dont use it in any process?

another Q, how I can calculate gate width using TonyPlot beside zoom in the structure. Is there any tools in TonyPlot to do it? I keep searching but fail to find what is the menu that I must click.

What is the SILVACO language that can calculate gate width (channel width)? I familiar with gate poly thickness command language but how I can calculte the channel width using the same method as to find the thickness?

Anyone working with INTEL here? suppose you should know how to use SILVACO

Mod's EDIT: Please use the EDIT button if there's no reply after your last post TQ

This post has been edited by almostthere: Oct 14 2005, 10:05 PM

have you tried using www.google.com to find your "SILVACO" solution?

I only finished Electrical&Electronic Engineering diploma level, 4 years ago. U guys are good in those logic gates. How i wish i could have more money to continue my studies to higer level. Too bad.

For a standard CMOS type transistor, NAND and NOR use 4 trannies, XOR uses 6-8 depending on implementation. AND and OR gates need an extra inverter, so that brings up the tranny count to 6.

NAND gates have an inherently better pull up output than NOR gates (the PMOS are in parallel in the NAND so less resistance).


It is not recommended to use more than 4 inputs per gate because the electrical characteristics of the gate deteriorates when more and more transistors are stringed together in series.

I don't think this thread was made for such questions.