isn't this under Digital Signal Processing topic? only know a bit(coz it's not part of my module )

Trying to make an ALU? Search for gate level schematics for the 74181 4-bit ALU, it's been copied to death by now so I guess that means it's pretty optimal

Thanx for the advice. I'm not sure if i wanna make into FPGA or not. THe primary goal is to come out a workable design under simulation, secondary is the FPGA implementation on Altera chip.
I've no idea about Convolution Coding Encoder


yup, I'm using Shift Register as input, but not barrel shifter. Multiply and Divide js need to shift 1 bit to left or right, so i js make it to shift when there's a clock. Well, I'm still thinking how to optimize the multiplier bcoz it takes me 16 cycles for an 8-bit MUL.


hehe, wat's CCT?

That's the lazy man's way of writing circuit.

Here you go ikanayam. That's my logic unit implementation to save some gates and also propagation delay.

The left one is my implementation, the right one is the conventional logic unit using MUX.


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Wow, you guys are good. Haven't been touching those since I got out of college two years ago....

This post has been edited by pillage2001: Oct 13 2005, 11:37 AM

lol, i got it now.

anyway, which adder do u think is more appropriate for my design.

8-bit Adder, might be expand to 16-bit or 32-bit in the future. Need to have a balance of power, die size and performance.

Currenly I'm using 2x 4-bit CLA ripple together to be an 8-bit one. I'm not sure if it is efficient enough when scale up to 32-bit.

I have 2 more choices : Carry Select Adder & 1 level CLA.

So which do u think is a better approach?
btw, I still have no idea to start designing a carry select adder, hahaha. Need to figure it out by today.

Well you can read up on booth encoding and canonical encoding, those might save you maybe a cycle or so, but if you want something really fast then you need to use an array multiplier/divider. Takes up a lot of extra hardware, but you can do the multiply/divide in a single clock (or maybe just a couple of clocks depending on implementation).

Hi, I am an E&E graduate as well and have been working for over a year. So far honestly what you guys have been discussing is something i am totally lost since I majored mostly in semiconductors. Even working as a R&D engineer, I hardly use any of those bits of electronics knowledge.

As for Discrete Signal processing, I think I can still remember some bits of my old Digital signal processing lectures though. Any questions about that?

I remember you... a couple of years back there was another bunch of EE students on LYN and we had threads like this too. You were at Newcastle, right? Graduated already... makes me feel even more like a dinosaur.

Thx for the tip on the ALU charge-n-go. I decided against integrating the AND and OR functions into my adder because it will make it easier for me to optimize the adder when i get down to the transistor level.

you can't really design an adder that's optimal for all sizes, because different adder types are more efficient for different adder sizes.
1 level CLA will be ridiculously big and unrealistic. You don't want to use gates with too many inputs. You might want to look into block CLA designs. They are much more efficient size wise and pretty fast.

Actually a well designed 2 level carry skip adder can be very fast and small compared to a lot of other designs. The trick is to get the skip blocks done right. You have to read up on how to determine the optimal skip block sizes.

Carry select adders are very hardware intensive, you end up about 3 times the amount of hardware as a simple adder. The speedup is pretty nice though.

That's the beauty of ECE, it's such a wide field. From software to hardware to physics. My focus is mostly in digital logic design and this stuff is what i love most. Smaller better faster.

ikanayam, thanx for yr advice. Well, i think i'll do some research on all kinds of adder. U know what, when i get the material online, cant really understand the transistor leve diagram bcoz i nv learnt b4 (pathetic ler my uni, nv teach )

Hehehe, we got the same taste. I m a noob in physical electronics stuff.

Transistor level circuits are pretty different from gate level circuits and generally they can be optimized a lot more. They don't always directly map to gate level stuff (OR gates might simply be replaced by wires joined together), so you do not want to look into the the transistor vs gate level stuff too much and get yourself confused.

I dunno anything like tat, hahah

btw, here's some stuff i get online


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Yeah, take a look at the carry skip/bypass adder, it's only a bit bigger and it's a nice speed improvement. You might want to look into that.

Yeah, but there is very little speed improvement at 8-bit, so don't think I can choose that. The project primary goal is to have a nice adder at 8-bit level, expandable nicely to higher bit is optional actually.

But i think Carry Select is out of question bcoz it's huge and takes a lot of power. Left only with CLA 1 level and my current design (4-bit CLA per block and ripple them together).

E&E Student here but taking Dip only
And still dont understand what my lecture teaches me

if i recall properly(kinda rusty a bit thx to those superb EDA tools that help u do the work), people normally use carry select in small scale(4 to 8 bits) and use CLA to cascade/expand to bigger word size(it's kinda optimized between speed and size)
don't bother about the input gates first, coz for me, i'll derive out the gates and switch all of them to NAND gate(or NOR, can be done using EDA tools). coz if you use too much different gates(AND, OR, NOR, NOT) together, you incur much higher cost(imagine the amount of ICs u need to use)

This post has been edited by X10A Freedom: Oct 13 2005, 05:41 PM

Hm... not sure i'm really getting what you're saying... why would using different gates incur higher cost? You can probably use less gates in total if you can use different gates than just 1 gate to generate all functions right?