Hey yeah...i was wondering the same thing to. Dual-core, Quad-core, Sex-Core, Octa-Core etc etc....

haha, sex-core --> one of the cores are dedicated for xxx processing, lol. btw, I have reliable sources that future generation CPU core doesnt not follow power of 2 (2, 4, 8, 16 etc...) Let's see how they will name 6 cores

they might use it you know. It's mathematically correct.

Yes, because TDP is tiered for servers. Go above 65 a little bit and boom, you're at 89/90.
Go above 90 (for Xeons), and Kaboom, 125. That's what the highend Penryn Xeon looks like (125W TDP, but a very practical guess should be <100W)

Just by a stepping Q6600 went from 105 to 95 (consumer markets normally don't use tiered TDPs as they don't need that buffered luxury that much) and I guess it's pretty tight around that too- older QXs, I don't know their stepping revs, but 130W (even a "loose" 110W) is a lot.

We only have Opteron TDPs. AMD could pull an Intel, get the consumer tri-cores at 75W or a non-standard rating just to make it look lower/closer to the real TDP it has (definitely more than 65W in high clocks, they can bin, squeeze BE chips, but that's out of the matter).


Iit's not like AMD's faultless too. They should have prioritized Barcelona more than Brisbane for 65 (it was nary a stopgap) but in the end, OEMs talk louder than anyone, and they do like cooler chips.

@Aoshi_88
Sex cores need ultimate protection. Pedal to the metal just ain't gonna work.
Butter?

This post has been edited by X.E.D: Sep 21 2007, 05:46 PM

Now.. never mind the G0 (which you obviously pulled out of thin air)... BUT when did B3 appear?

That's funny ya know because all the review units provided (and configured by AMD) are mostly B1s. Even the demo unit here in Japan is also B1? See http://www.watch.impress.co.jp/akiba/hotli...celonademo.html




Some benches of that demo PC here: http://www.xtremesystems.org/forums/showpo...30&postcount=48



So where are the B2 and the final production BA steppings? Are they available now or only begining of November (which is when Dell and HP announce shipments of Barcelona based servers)?

Errr... This is the first time I heard of the (fantasy) G0 stepping.

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Added on September 21, 2007, 6:07 pmAgreed, my BSmeter alarm was at a all time high there.

Do you realize that Intel had a very mature 65nm process compared to AMD? That is why they can bring down that TDP.

I disagree. OEMs like cheaper chips not cooler ones. They also want highly sell-able ("attractive" and cheap)




This post has been edited by lex: Sep 21 2007, 06:07 PM

HEX-core
hardcore & sexy edition

I'd hit that.


They'll almost certainly go by model numbers if there are going to be so many different configs. But then again marketing departments are... marketing departments.


Do you know why the TDP is like that these days? Why they don't have a specific TDP for each SKU?

lex, if the Core 2 Quad didn't have a G0, I'm seriously thinking about your google skills.

You're also assuming that AMD's 65nm isn't mature, while they've produced 65nm chips for a year already.
With 90nm they cut TDP tremendously months after release of the X2. AMD generally starts rougher, Intel starts more polished because after all, they ARE Chipzilla.

AMD might not want to bite what it can't chew. B2 for now is for the AM2+ Phenoms and upcoming newer Opterons 2/8300s. Coming November (earliest) so we have 2 more months to moan.

I think B1 and BA might be a BIOS flash away (microcode fixing the errata), but call that a conservative guess. Both of these chips are essentially the same, they won't clock higher.

This post has been edited by X.E.D: Sep 21 2007, 06:55 PM

I'm starting to get lost.

"Hardcore" would catch on quickly..

Me too... Quoted for reference....

I see... I thought you were referring to unreleased Barcelona steppings? Next time, be more specific...

The we have to wait and see, rather than trying to jump to (way off) conclusions on those Barcelonas, Phenoms and tri-cores.

hey... phenoms wont use am2 socket rite?
should be on am2+????
i want to upgrade my gc,mobo,proc...
so all my cpu suing high end stuff haha

Network Engineering FTW... Too bad i didn't take EEE for my degree.

You know, that comparison really felt like the gap between the Marines... and everything else in the Army.

i don think it will use same socket... and i also won say AM2+...

i think it will be optimized for ATI chipset based mobos... so bye bye nForce and the rest...

AM2+ CPU can be slot into AM2 sockets.

However, you will have 2 issues (quite confirmed I think)
1. Lack of HT3.0. This might be instrumental, as how the K10 uses the L3 victim cache and the extra latency, HTT speeds might matter.

2. This one is more crucial- your memory controller speed. For mobos without Split power plane (AM2+) support, your IMC will run *even* more slower than the CPU (it already does in K10, by 100-200Mhz). Might affect performance for all it's worth.


To be honest, the new RD790 mobos should be good and hopefully, also cheap (single card versions FTW). It should be the easiest chipset for AMD overclocking period. (Not like it wasn't easy using ClockGen anyway/ )

AM2+ is more like new specification or standard. Regarding the socket design, it's identical to AM2 and backward compatible.

I don't think they will come out with 6 cores... Maybe they will jump straight to 8... but anyway, I was shock to when AMD has a 3 cores processor... I am more interested how will they name 5 cores than... but... will there be a 5 cores processor?

When you do MCMs they better be symmetrical.

So on 4-core die, the only other possibility would be sex.

why not
since amd dare to make 3 core
cheaper than quad core

haha
maybe i just change my mobo then

currently use chap lang one
so simply sell it to other ppl
or give it to my bro
and get a brand new rd790
a high end 1

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Added on September 23, 2007, 12:33 am

wrong section... haha

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Added on September 23, 2007, 12:34 am

oso wrong topic 1 haha

This post has been edited by nelienuxe_sara: Sep 24 2007, 04:45 AM

It's just the bus interface, it's kind of hard to pull any seekrit tricks since if someone else has your bus license, they will have the full specifications to your bus.


1. For single chip configs, the HTT speed will probably not be an issue because there is no coherency traffic to worry about. The memory controller is integrated, so all memory traffic goes through there. HTT only handles I/O, and it's probably not a bottleneck even in the majority of cases.

2. I don't think a 1600MHz -> 1800MHz memory controller will make that much of a difference. Especially when your base memory clocks are much much lower than that.


They really don't have to be symmetrical, especially if you want to maximize yields on many many core dies in the future.