You guys forgot about the sub-Q6600 market.

Market demand is a LOT less in the Q6600 area (even when it's that cheap), most people would pay RM500-600 for a decent mid/high chip, no more.

X3 could be that possibility, clock the chips higher, price them lower, they have the flexibility to do so- as these weren't even supposed to be actual retail chips.

That said, I'd like to see Intel responding with an even cheaper quaddie. And also cut the darn platform price too.

On NCIX it's ~950 ringgits, that's precisely where the cheapest 6600 batches retail for now.
And 20% less at stock, not really what the general consumer's buying.

What I'm implying is that AMD *can* afford to price these low (even possibly C2D low) and clock them 10%+ higher than a relative C2D.
Single threaded performance it should win (extra clocks), multi threaded performance it would win (3 vs 2 + K10 does look happier on core scaling)

The X3 isn't targeting the C2Q market- it's locking on to the E4300-6850s we buy today.


(Note: 3 cores > 2 cores in promotion, OEMs might actually snatch these chips faster than the retail channel would)

This post has been edited by X.E.D: Sep 18 2007, 06:37 PM

30% theoratically- but there are a lot of 'buts' I think.
1- AMD should be taking the Intel Core approach to all its CPUs- all the same model, bin and cut. This would equate to much higher yields than 30% even on the fully functional QC units on the long term, and hidden cost savings in getting a unified chip to all SKUs. Once 65 matures to AMD's sweet spot (their later steppings are quite good, evidenced by their 90 work) they won't have that much of a problem competing.

2- It should improve by time- getting unified (I don't know if Kuma is even native dual or cut-down quad) might also get clocks to competitive speeds, even in dual/tri cut-down scenarios. If AMD can get production of 3.2Gigas (B2 Max, B3 is currently unknown) before Q2 ends, kudos to 'em.

3- C2Qs are only made cheaper nowadays because Core manufacturing is already rather mature at the 65 level, plus the retooling to 45 CMOS they would have no incentive to price that high for even the base chip (Note the Q6700 is still there for margin suckers lol)


ps: Shanghai could make it considerably smaller (<200?), if they get hi-k dielectrics they'd be on even ground with Penryn clock wise. (Yet the fact that AMD's collab with IBM on SiGe on 65 might indicate that they're delaying it.)

This post has been edited by X.E.D: Sep 18 2007, 10:49 PM

I hate quoting and unquoting so I'll reply in whole lol.
Mario was referencing to the delay of Barcey more than the currently disproportionate performance ad/cost disadvantages. Dual Kuma would be a good proposition, but that would just make them play the manufacturing game once more- and lose. And servers won't like it (Everyone hated 4X4 v1, face it )

So far we've seen B0 at 1.6, B1 at 1.9,2.0 and 2.5 (a clock it's not supposed to run at), B2 maxes out at 3.2 and 3.4 for quad/duals respectively (cherry picked you may argue, but this is the first production stepping, want to compare- compare it to the first X2s. The 3.33Ghz Yorkfield by all means might be too.)

AMD did NOT tape out Brisbane >2.6 (though OCs to 3+Ghz was quite feasible) because it's useless then- Intel counters with higher clocks/price drop, your ASPs dive, your next chip is held on an even higher clock bar to compete with. They went for IPC first, and IMO the only feasible solution.

45 is solely a roadmap thing- they should have taped it out by Q4 if it were to happen. AMD might go SiGe on K10 (10.5 too) and for Bulldozer, revert back to CMOS- since "ATI" chips are still using that, Fusion might be easier to do.

Their point for 65nm was EE- 65W and below.

89W TDP 3.2 could be possible (strict binning like 90 F3 does) but in the end, what's the motif for launching a product at the top bin when it should be costly and not even win over the buyers of Core 2s (people spending that much tend to OC, and compared to a 65W C2D it doesn't bode well to OEMs)


I have a strong feeling that this could go up to say, 2.6 in B2 and still be 65W (X4 will be 89).

It's 95W @ B1. B2 is the "miracle" stepping (no, I didn't dub that ) that's why Phenom FXes and real production Barcelonas (not early revs) start from B2.

Currently highest known B2 speeds are 3.2/3.4 so it is possible, given some maturation time and newer spins.

I was mentioning X3s. Tris could fit in 65W ACP (lol) with B2, but I think the breakneck speed will be 2.6 where it'll be classified 90 even if it uses a little bit more.

BA = Fixed some errata ver. of B1 (probably microcode) so it scales the same.

Anand's "B2"s were B1s. Every site pre Barcelona launch were given B1s (not BAs, B1s) With overvolt of course, you'd get 2.5Ghz out of those, but in general BA/B1 can't scale nicely above 2Ghz.

You've seen all the Phenoms at 3Ghz. Fudo had it at 3.2 and 3.4 as the max speeds the B2s would go (forgot if voltmods were applied or not)- these should be the AM2+ chips without coherent HTT, for Opterons I'll give 2.6 a rather high bin.

For my "speculations", I give you 2 letters: G0.

You really didn't get it, didn't ya?

B3 -> G0. What exactly happened to the thermals... I dunno.

Truth is, you're basing the whole future of a chip on a preproduction stepping. If you need to voltmod to 2.5, that's pretty bad and reeks of B1 (when B2 can run off air, you'd ROFL at such a big voltmod for 2.5 if it were)

Barcey B1 2Ghz doesn't go up to 90. Server thermals are very airy and you know that too.

This post has been edited by X.E.D: Sep 21 2007, 06:46 AM

Yes, because TDP is tiered for servers. Go above 65 a little bit and boom, you're at 89/90.
Go above 90 (for Xeons), and Kaboom, 125. That's what the highend Penryn Xeon looks like (125W TDP, but a very practical guess should be <100W)

Just by a stepping Q6600 went from 105 to 95 (consumer markets normally don't use tiered TDPs as they don't need that buffered luxury that much) and I guess it's pretty tight around that too- older QXs, I don't know their stepping revs, but 130W (even a "loose" 110W) is a lot.

We only have Opteron TDPs. AMD could pull an Intel, get the consumer tri-cores at 75W or a non-standard rating just to make it look lower/closer to the real TDP it has (definitely more than 65W in high clocks, they can bin, squeeze BE chips, but that's out of the matter).


Iit's not like AMD's faultless too. They should have prioritized Barcelona more than Brisbane for 65 (it was nary a stopgap) but in the end, OEMs talk louder than anyone, and they do like cooler chips.

@Aoshi_88
Sex cores need ultimate protection. Pedal to the metal just ain't gonna work.
Butter?

This post has been edited by X.E.D: Sep 21 2007, 05:46 PM

lex, if the Core 2 Quad didn't have a G0, I'm seriously thinking about your google skills.

You're also assuming that AMD's 65nm isn't mature, while they've produced 65nm chips for a year already.
With 90nm they cut TDP tremendously months after release of the X2. AMD generally starts rougher, Intel starts more polished because after all, they ARE Chipzilla.

AMD might not want to bite what it can't chew. B2 for now is for the AM2+ Phenoms and upcoming newer Opterons 2/8300s. Coming November (earliest) so we have 2 more months to moan.

I think B1 and BA might be a BIOS flash away (microcode fixing the errata), but call that a conservative guess. Both of these chips are essentially the same, they won't clock higher.

This post has been edited by X.E.D: Sep 21 2007, 06:55 PM

You know, that comparison really felt like the gap between the Marines... and everything else in the Army.

AM2+ CPU can be slot into AM2 sockets.

However, you will have 2 issues (quite confirmed I think)
1. Lack of HT3.0. This might be instrumental, as how the K10 uses the L3 victim cache and the extra latency, HTT speeds might matter.

2. This one is more crucial- your memory controller speed. For mobos without Split power plane (AM2+) support, your IMC will run *even* more slower than the CPU (it already does in K10, by 100-200Mhz). Might affect performance for all it's worth.


To be honest, the new RD790 mobos should be good and hopefully, also cheap (single card versions FTW). It should be the easiest chipset for AMD overclocking period. (Not like it wasn't easy using ClockGen anyway/ )

When you do MCMs they better be symmetrical.

So on 4-core die, the only other possibility would be sex.