Hate to reopen the can of worm marked expired.

But just to share my thoughts of the likelihood of "local storage" being cache. First, I do not think that IBM would called cache as local storage. I think local storage is more of a SPE internal RAM. An internal RAM would typically be refered to as a local storage.

Secondly, Having so many SPU units (8 in total based on the diagram), it would mean 256Kx8 L1 cache. A 2MB cache would bump up the price of the PS3 to preposterous level.

But I'm not claiming that the SPE has no L1 cache. On the contrary, I think that we might be looking at a very top level block diagram ( a macro view is you like ) and that the cache (if ever there be one) is embedded into one of this block (probably the SXU).

Again, I stress, this is all speculative. Constructive feedback welcomed.

At the time of writing I've also got this from gamespot:

1 Core, 7 x SPE 3.2GHz (256KB SRAM per SPE), 7 x 128b 128 SIMD GPRs
http://hardware.gamespot.com/Sony-PlayStation-3-15015-S-4-4

SRAM. If this is true, we could safely assert that the local storage is certainly not L1 cache. It could still be L2 cache, but I think it's most likely just that, internal RAM

Also spot this interesting bit after the above edit. On the L2 Cache row has this bit of info:
512KB L2 cache, 256KB per SPE

Yes, it's 1am and I'm still writing this shite.

This post has been edited by ray_: May 30 2005, 01:09 AM

Well here's what i think. It's a cache of some sort, call it whatever you want. The purpose of this cache is to provide high bandwith to the SPE units because they are streaming data processors and the initial latency (probably higher than that of a typical L1/L2 cache) will not matter that much because the SPE is a streaming data processor. Look under the definition of "cache", it does not have any specific details about how it should be implemented. Cache and local memory are loosely interchangeable terms.

I believe adding more cache to a CPU is a lot cheaper than adding more logic. Cache is typically densely packed and cheap to manufacture. A 2MB cache on the P4 6xx series does not bump the price up to preposterous levels at all.

It's too late to write a rebuttal. But do expect one in the morning.

First, let me get to some points:

1) I've suspected that the local storage is indeed not L1 cache.
If the tech. spec. at gamespot is anything to go by, thenI would say that my suspicion is correct. The local storage is infact a L2 cache according to gamespot.

2) I've suspected that the local storage is in fact internal memory.
Again, if gamespot is correct, then I would be wrong. Cell's "Local storage" isn't internal RAM. Although I agree that the line has blurred somewhat. I still think that there's a fundamental difference between RAM (memory) and cache. Cache has additional logic to invalidate, flush and enable/disable it's cells. Also the hybrid set-associative cache is only addressable by the CPU and "associates" each memory region of the cache with an equivalent region of the external RAM. Memory works differently to cache.

I do not think that cache is cheap. Cache, especially fast L1/L2 cache running at core frequency, are really expensive to make, but it does gets cheaper as the technology improves. That is why there is so very little of cache RAM available on all off-the-shelf processors. If you goggle "cache" and click through the result, it would almost always be tagged with the word "expensive".

Although it might be densely packed, cache would still take a large portion of the die. The Cell has a 512K L2 cache. Look at how much space it requires on the die layout.

First, let's share what google brought me this morning: microprocessor report article

In that report, it is written that SPEs do not have cache, and we can infer that the LS is indeed not an L1 cache. But why do you have this fixation on L1 anyway?

The LS is SRAM, it sits right next to the SPE's logic and execution units. With that kind of placement it probably runs at the same clock frequency (or perhaps matched with the pipeline latency for read/writes to save power?) That's probably all that the LS have in common with cache.

I've also mentioned earlier that cache is only effective when there is locality to be exploited. When there is no locality, cache misses are so expensive that it's better not to have them there in the first place. Cache adds an element of unpredictability to programming; Cache misses are inevitable and the programmer has no direct control over when they happen. This sort of unpredictability is a no-no in realtime applications. Graphics rendering in games can be classified as realtime, because they have a 1/60 second deadline for all their processing.

The LS of each SPE can be mapped into system memory. Which means that LS is visible to the programmer. A cache is invisible to the programmer, it has no implicit memory address range.

After all this discussion on the SPE, we seem to have left out the PPE which is a traditional 64-bit processor, and has its own L1 data and instruction cache.

Again, thanks for the wonderful link.

My fixation on the L1 cache was due to your claim that "Local storage" was infact a L1 cache. Which has now been proven to be incorrect. I think you should give me that much.

I share some of your argument on my most recent post (eg. the fact that cache is not directly addressable by the user). Please read em' and see if you'd agree.

For context:

Fed my own medicine, gah! In hindsight that was a rather naive conclusion based on the observation that the LS consists of SRAM (as are all low-level caches), is geographically close to the SPU and (maybe) runs at core frequency. If I wanted to cover my backside, I could retort that by using the word "effectively", I wasn't too convinced of it being L1 cache even back then, but that would make me look small, so I won't.

So, can we safely agree that the Local Store memory of 256K on each SPE is neither L1 nor L2 cache, and doesn't need to be?

WRT to cache implementation and cost:

The fastest caches are implemented in SRAM, which iirc, take 6 transistors to implement a single cell. They are certainly not as dense as DRAM. A common convention for calculating gate counts is to take the number of transistors to implement a NAND gate, in CMOS processes, that is 4 transistors. That gives us a 3:2 transistor ratio, ie for every 2 SRAM cells we could have had 3 logic cells. Let's see you guys bake your noodles on that tid-bit.

I'd like to add that n-way set associativity isn't the only way to make a cache. Direct mapping does not require the sort of logic complexity that we see in the L2 in the die photos. Sure, nobody wants to use direct mapped caches anymore today, but computer architecture trends tend to make a full circle every couple of decades. We're seeing stack machines and VMs making a re-appearance lately even though they were supposed to have died off in the 70s and 80s. That said, we should not write off any technique even though it looks sub-obtimal based on today's performance metrics/requirements.

Reading the document, it looks like the SPE has no cache at all. And that the local storage is rather quite simplistic in design. And also that Gamespot is inaccurate in labeling local storage as L2 cache.

I think here's how it would work:

- Prior to running a specific process on the SPE, all instructions and data required for the process would need to be copied to the SPE local storage via the PPE MMU. This should be done either autonomously by a robust compiler (supplied by the PS3 dev. kit) or by the programmer (gasp...).

There are no mentions of the speed at which the SRAM is running. But since SRAM are traditionally asynchronous, there would be wait cycles required for read and write accesses.

There are also no mentions on whether the SPE DMA could directly address external memory space or I/O address space to transfer instruction or data from external memory or I/O memory mapped peripherals to the local store.

This post has been edited by ray_: May 30 2005, 11:58 AM

next gen consoles discussion + next gen pc discussion

i prefer Sony

"like.no.other"

ok but a single NAND gate is not really useful. It takes many such gates to make a unit that is capable of doing an operation. These gates have to be wired up to each other. And usually logic is less consistent in terms of size and shape, which makes it take up more die area per transistor compared to SRAM cells. Die area = manufacturing cost.

Just look at a die photo of the Northwood CPU. The L2 cache alone is practically half of the total transistor count (25.2 million transistors out of 55 million, 46%). Yet it takes nowhere near half of the die area on the chip.

- Famitsu Weekly has conducted a next generation reader survey, to see which console system the readers are most interested.

Most Interested Next Generation Console
1. Nintendo Revolution - 42.2%
2. Sony PlayStation 3 - 39.8%
3. Microsoft Xbox 360 - 18.0%

Why do you like Revolution?
- Compact design, typical Nintendo style
- Able to download Famicom (NES), SFC (SNES) and Nintendo 64 games
- Possible innovative / new designs in Revolution
- Confidence in the hardware

Why do you like PlayStation 3?
- Outstanding technical specifications, standout against other next generation consoles
- Downward compatibility with PSone and PlayStation 2
- Cell processor and Bluray support are unique to the console
- Like the design of the console (but the controller design is crazy)

Why do you like Xbox 360?
- Developer support is splendid, especial people like Akira Toriyama and Sakaguchi.
- Square Enix supports the console
- Positive console design, color, technical specs and software lineup
- Console can stand vertically



link=http://www.the-magicbox.com/gaming.htm

looks like nintendo really has very strong influence in japan compared to ps3

looks like xbox is still doing not so good in japan

Readers polls means nothing. After 1 year of the console launch, then you can gauge whether it's a success or a bomb. Despite all the "readers vote" for Revolution, there's almost without a doubt the PS3 will outsells it.

oooooh, MS IS DOOMED!!!

i agree wif Matrix, reader polls means diddly squat~

besides, i think even wif 18%, MS should be more than happy wif dat liao... if its achievable that is

well,reader poll can count as early indicator,but i agree with 18%,thats higher then xbox

Beeeep!!! Wrong answer!

Winning Eleven is also known as Pro Evolution soccer for the Western market and is available for the XBOX and PC (but the PC might not have latest version).

u ask him and see...

readers poll might means little now.. but it is an early indication of what the gamers think after e3 and stuff..

Next-gen leaders talk about their consoles
Microsoft senior vice president and chief Xbox officer Robert J. Bach, Sony Computer Entertainment president Ken Kutaragi, and Nintendo president Satoru Iwata.

Interesting read i must say...

i saw that but i wonder how does those 3 people sit together even tough they are rival