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 Next Gen Console: PS3 vs XBOX 360 vs. Wii, Next Gen speculation discussion

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ray_
post Jun 6 2005, 12:05 AM

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QUOTE(silkworm @ Jun 4 2005, 12:17 AM)
Quite a logical definition, but perhaps a bit narrow. For physically small or resource limited systems, this rings true. However, once certain criteria of performance (CPU/RAM) and user interface are met, an embedded system is entirely capable of self-hosting its development environment. For instance, one needs a decent method of character input, a screen that displays a reasonable amount of text, and storage for the source files and compilation tools.  My example of the "embedded PC" above could be one such system.
*
The more I think of the term "embedded PC", the more it sounds like an oxymoron. biggrin.gif Production lines do have systems doing specialized function. But they'd probably have a few specialized HW and real-time constraints, and thus would be suitably associated to embedded system rather than PC. They could probably be reconfigured to run spreadsheets, but they wouldn't do it as well.

Having written my version of what constitutes an embedded system, I was reminded of the Agilent Logic Analyzer that sits at my cube not so long ago. It's an embedded system no doubt, but it has also a Linux kernel and thus could build and run application on board.

I guess there isn't one all encompassing definition for an embedded system. But the concensus seems to be that the next gen. consoles would still be firmly rooted as embedded systems, until they start sprouting spreadsheets and word processors (i.e. be capable of general purpose computing).

And no H@H@, don't move Adidas shoes to computer. smile.gif
ikanayam
post Jun 6 2005, 03:48 AM

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QUOTE(ray_ @ Jun 5 2005, 11:05 AM)
I guess there isn't one all encompassing definition for an embedded system. But the concensus seems to be that the next gen. consoles would still be firmly rooted as embedded systems, until they start sprouting spreadsheets and word processors (i.e. be capable of general purpose computing).
*
Yes, the console itself may be considered an embedded system. But the CPU cores used are general purpose cores. They could be used in servers or desktop computers if someone wanted to do it.
SUSMatrix
post Jun 13 2005, 09:36 AM

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Oooi...why no debate here last few days one?? Must be running out of rumours and news and steams liao...

btw, to all those techie gurus, i just wanna ask this:

Why do you think the PS3 CELL has 1 "redundant SPE" and runs 25GFlops(theorotically) less?? IMO, redundant means FAULTY. SONY must be having headache trying to get enough good yield to get all 8 SPE working and thus probably getting a high % of literally.."half baked"..sillicons with one SPE still "uncooked"(or toasted...whichever u prefer...hee-hee).

I remember previously that SONY mentioned that the CELL will not be ready in time for the PS3, but obviously they squeeze the chip development schedule ahead to make the CELL ready for the PS3, but in turn have to sacrifice some time to further fine tune and improve the design and also the time needed for the manufacturing process to get mature to have high % of good yield.

So their best bet would be going for 7 SPE, which in their opinion is achievable without throwing away too many CELL chips (those < 7 SPE working).

Maybe a year or two later, they'll have a good enough manufacturing process to get enough good yield for 8 working SPE, then we have an 8 SPE PS3?

As for XBOX360, I think ATI unified shader is very interesting and certainly sounds a lot more flexible than Nvidia "Dual SLI GT6xxxx on a chip". But there's a rumour that the shaders can only do EITHER pixel or vertex shader PER CYCLE, meaning it's not as flexible as it seems, anyone have any more info about this?

Okay...finally the PS4!! Okay, i'm a bit far ahead, but if the CELL proves successful, in another 6 years time, the manufacturing process will be good, the design has improve and they can make lots of CELL chip at rock bottom prices. And since the CELL is all multi CPU ready. The # of SPE can also increase per CELL CPU by then. By just packing in a couple of cheap CELL chips, they'll have the next PS a real powerhouse at a cheap price...which i think that's when their CELL hardware investment really pays off.(but of course, the PS3 would have guarantee them some ROI in terms of software royalty and other potential electronic products(TOSHIBA washing machine!!! Oh yeah, the next TOSHIBA washing machine will have a GIGABIT network port and linkable to your PS3!! Maybe you can control the swirling motion of the water from your PS3 BATARANG!! J/K) might give some cash back also)..after all, the according to IBM/SONY/Toshiba, the CELL was designed to cater for the next 10 years or so.

Still, currently, the CELL as it is, sounds good ( the multi SPE) but at the same time, it's a IN-ORDER CPU (like the XBOX360 PPC CPU also), which is much less complicated than Intel/AMD CPU's for PCs which is OUT OF ORDER CPU. I think OOO CPU is more powerful as it can predict instructions and acts accordingly while, IO CPU is simplistic and just acts on whatever it's fed.

Of course the benefit of the IO CPU is reduced size, meaning less HEAT and faster requency...so you can't exactly compare a PPC or Intel chip running at 3.2Ghz to a 3.2Ghz CELL.

Thus in order to fully utilize the CELL CPU, the PS3 archictecture have to have a huge bandwidth and streamline the instructions to the SPE via the Power PC core(what do they call that? PPE?), I've no idea how are they intending to overcome the shortcoming of the in-order instruction sets, but most likely, like it's predecessor, the EE and GS chip, by some the force of raw brute bandwidth, which hopefully is enough to feed it optimally.(the CELL is sorta evolution and further improvement from the EE/GS combo me thinks).

Finally a stab at the SPECS. All those bally-hoo about 2 TERAFLOPS ...but no mention on whether it is single precision or double precision..no mention of how the benchmark was done...same for MS. Basically, both are crappio marketing scheme.

I believe the CELL will be adequately powerful, but i don't buy it to be THAT powerful...just like the EE/GS back in it's time. But i think the real payoff of the CELL is not now, but the next 5 years, when the manufacturing process has improved and design has been further finetune and when multiple cheap CELLS are easily available and linkable in a single motherboard to power the washing machine, TV, fridge,steam iron and whatelse...PS4..smile.gif

Okay guys...shoot away. smile.gif


ray_
post Jun 13 2005, 11:53 PM

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QUOTE(Matrix @ Jun 13 2005, 09:36 AM)
Oooi...why no debate here last few days one?? Must be running out of rumours and news and steams liao...

btw, to all those techie gurus, i just wanna ask this:

Why do you think the PS3 CELL has 1 "redundant SPE" and runs 25GFlops(theorotically) less?? IMO, redundant means FAULTY. SONY must be having headache trying to get enough good yield to get all 8 SPE working and thus probably getting a high % of literally.."half baked"..sillicons with one SPE still "uncooked"(or toasted...whichever u prefer...hee-hee).

I remember previously that SONY mentioned that the CELL will not be ready in time for the PS3, but obviously they squeeze the chip development schedule ahead to make the CELL ready for the PS3, but in turn have to sacrifice some time to further fine tune and improve the design and also the time needed for the manufacturing process to get mature to have high % of good yield.

So their best bet would be going for 7 SPE, which in their opinion is achievable without throwing away too many CELL chips (those < 7 SPE working).

Maybe a year or two later, they'll have a good enough manufacturing process to get enough good yield for 8 working SPE, then we have an 8 SPE PS3?

As for XBOX360, I think ATI unified shader is very interesting and certainly sounds a lot more flexible than Nvidia "Dual SLI GT6xxxx on a chip". But there's a rumour that the shaders can only do EITHER pixel or vertex shader PER CYCLE, meaning it's not as flexible as it seems, anyone have any more info about this?

Okay...finally the PS4!! Okay, i'm a bit far ahead, but if the CELL proves successful,  in another 6 years time, the manufacturing process will be good, the design has improve and they can make lots of CELL chip at rock bottom prices. And since the CELL is all multi CPU ready. The # of SPE can also increase per CELL CPU by then. By just packing in a couple of cheap CELL chips, they'll have the next PS a real powerhouse at a cheap price...which i think that's when their CELL hardware investment really pays off.(but of course, the PS3 would have guarantee them some ROI in terms of software royalty and other potential electronic products(TOSHIBA washing machine!!! Oh yeah, the next TOSHIBA washing machine will have a GIGABIT network port and linkable to your PS3!! Maybe you can control the swirling motion of the water from your PS3 BATARANG!! J/K) might give some cash back also)..after all, the according to IBM/SONY/Toshiba, the CELL was designed to cater for the next 10 years or so.

Still, currently, the CELL as it is, sounds good ( the multi SPE) but at the same time, it's a IN-ORDER CPU (like the XBOX360 PPC CPU also), which is much less complicated than Intel/AMD CPU's for PCs which is OUT OF ORDER CPU. I think OOO CPU is more powerful as it can predict instructions and acts accordingly while, IO CPU is simplistic and just acts on whatever it's fed.

Of course the benefit of the IO CPU is reduced size, meaning less HEAT and faster requency...so you can't exactly compare a PPC or Intel chip running at 3.2Ghz to a 3.2Ghz CELL.

Thus in order to fully utilize the CELL CPU, the PS3 archictecture have to have a huge bandwidth and streamline the instructions to the SPE via the Power PC core(what do they call that? PPE?), I've no idea how are they intending to overcome the shortcoming of the in-order instruction sets, but most likely, like it's predecessor, the EE and GS chip, by some the force of raw brute bandwidth, which hopefully is enough to feed it optimally.(the CELL is sorta evolution and further improvement from the EE/GS combo me thinks).

Finally a stab at the SPECS. All those bally-hoo about 2 TERAFLOPS ...but no mention on whether it is single precision or double precision..no mention of how the benchmark was done...same for MS. Basically, both are crappio marketing scheme.

I believe the CELL will be adequately powerful, but i don't buy it to be THAT powerful...just like the EE/GS back in it's time. But i think the real payoff of the CELL is not now, but the next 5 years, when the manufacturing process has improved and design has been further finetune and when multiple cheap CELLS are easily available and linkable in a single motherboard to power the washing machine, TV, fridge,steam iron and whatelse...PS4..smile.gif

Okay guys...shoot away. smile.gif
*
Nice post. thumbup.gif

Well... this is more geared towards solid state junkies. So perhaps ikanayam or Silkworm could comment (especially the part on IO and OOO). I'll pass on most but a couple of these. smile.gif

Just a note on redundancy. It's there to provide fail-safe operation, thus is not really a fault by itself. Could you direct us to the source of that information, it''ll interesting to know that Sony is packing up 9 SPEs to provide improved yield, something unheard of (by me at least) so far.

The point on the SPE "streamlining" instructions from the PPE is not exactly correct. Like we've said before, prior to executing any task on the SPE, all data and instructions had to be copied into the LS. This should be done using the dedicated DMA of the SPE via memory spaces mapped by the TLB/SLB of the PPE MMU. So there would be no data or instruction fetch from the external memory, instead instruction and data would be fetched from the internal memory (i.e. Local Storage) and executed in a timely manner given the proximity and the speed of the SRAM. I do not however know if the internal bus would introduce any redundancies. If ever there be, I'm sure we will be looking at an insignificantly small figure.
silkworm
post Jun 14 2005, 05:38 PM

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QUOTE(matrix)
Still, currently, the CELL as it is, sounds good ( the multi SPE) but at the same time, it's a IN-ORDER CPU (like the XBOX360 PPC CPU also), which is much less complicated than Intel/AMD CPU's for PCs which is OUT OF ORDER CPU. I think OOO CPU is more powerful as it can predict instructions and acts accordingly while, IO CPU is simplistic and just acts on whatever it's fed.
You are confused. The purpose of OoO is not to predict, but rather to exploit more instruction level parallelism out of a pipeline. There are basically two major drawbacks to a pipelined structure: data dependancy/hazards and pipeline flushes due to branches. Pipeline flushes affect the whole pipe from the point where the branch is taken and are generally more "expensive" in terms of lost performance. They are countered by branch prediction, which the PPE and SPEs of Cell do have.

Data hazards such as Read-after-Write(RAW), Write-after-Read (WAR), and Write-after-Write (WAW), stall a pipeline by inserting "bubbles" in the pipeline until the dependancies have been solved, at the cost of a few cycles. Out-of-Order Execution may help in special cases where there are enough operands available in the instruction stream to feed to an execution unit, so that the processor can go ahead and execute that instruction while another (earlier) instruction is still waiting for its data to be ready. Sort of like in a bank, if a customer is at the counter and he's busy filling out a form, the teller will ask the next customer to come to the counter, provided that this next customer doesn't need to fill any forms.

Even without OoO, a pipeline is still equipped with data forwarding buffers to minimize length of pipeline stalls. A forwarding buffer "forwards" the result of the execution units to the earlier stages of the pipeline so that those results may be used by following instructions that depend on it, instead of having to wait for it to be written to memory and fetched again. Furthermore, instruction re-ordering and scheduling is also within the capabilities of modern optimizing compilers. Put these two together and pipeline stalls are a non-issue with careful programming.

OoO is "expensive" to implement in terms of complexity and silicon area. In order (pun not intended) to find a suitable instruction to execute out-of-order, the decoded instruction buffer should be quite large. Look at the P4's Netburst micro architecture, their "L1" trace-cache is filled entirely with decoded micro-ops, which the OoO engine can search through to find a suitable candidate for scheduling. The further ahead the OoO engine grabs the instruction from, the larger the re-ordering buffer needs to be; instructions still need to be retired in order. The kind of silicon area that takes up could be put to different use, and in the case of the PPE in the Cell CPU, it looks like it's been taken up by Simultaneous Multi-Threading (SMT).

SMT is another strategy to make efficient use of the execution units in a CPU, at the cost of doubling the necessary units for thread context (Instruction Pointer, Stack, Flags, GPRs), when one thread is using the Adder, another can be using the Load-Store Unit, or the FP unit.

In summary, OoO is not a magic bullet that promises huge performance gains just by being featured in a CPU's architecture. It's not a new idea either, ironically it was used first by IBM in the 1960s, as shown in this research paper. The designers of Cell have made traded off this feature with other architectural features like SMT, dual-issue pipelines, etc to attain a balance that is acceptable to them, and hopefully suitable for the intended application, namely console gaming.
SUSMatrix
post Jun 15 2005, 09:08 AM

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Thanks to Silkworm and Ray for some explanation....i don't pretend to understand everything Silkworm put up there...maybe 30% smile.gif, but good enough for me.

So that means the PPC and CELL has "branch prediction" which achieves similar results to OOO execution, rite?

QUOTE
Could you direct us to the source of that information, it''ll interesting to know that Sony is packing up 9 SPEs to provide improved yield, something unheard of (by me at least) so far
9 SPE? No, i was saying 7 SPE. It is in the official PS3 SPECS all over the web. It's mentioned "1 SPE reserved for redundancy" or something like that.

Added:

Here's a nice link for reading the CELL...haven't finish reading it myself...hurts my head...LOL.

http://www-306.ibm.com/chips/techlib/techl...icle-021405.pdf

This post has been edited by Matrix: Jun 15 2005, 02:25 PM
ray_
post Jun 16 2005, 01:17 PM

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QUOTE(Matrix @ Jun 15 2005, 09:08 AM)
Thanks to Silkworm and Ray for some explanation....i don't pretend to understand everything Silkworm put up there...maybe 30% smile.gif, but good enough for me.

So that means the PPC and CELL has "branch prediction" which achieves similar results to OOO execution, rite?
9 SPE? No, i was saying 7 SPE. It is in the official PS3 SPECS all over the web. It's mentioned "1 SPE reserved for redundancy" or something like that.

Added:

Here's a nice link for reading the CELL...haven't finish reading it myself...hurts my head...LOL.

http://www-306.ibm.com/chips/techlib/techl...icle-021405.pdf
*
I think if what you've said in regards to redundancy is true, I would presume that the redundant SPE is there to be swapped in when all 7 SPEs are swarmed to maintain throughput. Or, a non-maskable error such as alignment faults is causing one of the SPE to be decommissioned until it's reset.

I would anticipate a new programming paradigm for Cell. Well, at least for the developer of the Cell's RTOS. God forbid that the memory management of the SPE would ever be passed into the hands of the application developer.

Actually, I would anticipate a few scenarios that could be implemented into the memory management portion of the SPE in the RTOS:
1) Each SPE's task footprint would be made small enough to fit into the 256K LS. Task would be queued in a shared virtual task pipe and fed into the SPE based on either first-come-first-served basis, round-robin or priority scheduling. Any any rate, there would be frequent memory swap accomodated by the PPE MMU.
2) Each SPE would be assigned its own dedicated virtual task pipe and fed into the SPE based on either first-come-first-served basis, round-robin or priority scheduling. Memory swap is accomodated by the PPE MMU.
3) There aren't enough task to load all 7 SPEs and the redundant SPE(s) could be programmed to power the PS3 grill as required. (*yum...)
ikanayam
post Jun 16 2005, 01:27 PM

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QUOTE(Matrix @ Jun 14 2005, 08:08 PM)
Thanks to Silkworm and Ray for some explanation....i don't pretend to understand everything Silkworm put up there...maybe 30% smile.gif, but good enough for me.

So that means the PPC and CELL has "branch prediction" which achieves similar results to OOO execution, rite?
9 SPE? No, i was saying 7 SPE. It is in the official PS3 SPECS all over the web. It's mentioned "1 SPE reserved for redundancy" or something like that.

Added:

Here's a nice link for reading the CELL...haven't finish reading it myself...hurts my head...LOL.

http://www-306.ibm.com/chips/techlib/techl...icle-021405.pdf
*
Branch prediction and OOO are different things.




QUOTE(ray_ @ Jun 16 2005, 12:17 AM)
I think if what you've said in regards to redundancy is true, I would presume that the redundant SPE is there to be swapped in when all 7 SPEs are swarmed to maintain throughput. Or, a non-maskable error such as alignment faults is causing one of the SPE to be decommissioned until it's reset.

I would anticipate a new programming paradigm for Cell. Well, at least for the developer of the Cell's RTOS. God forbid that the memory management of the SPE  would ever be passed into the hands of the application developer.

Actually, I would anticipate a few scenarios that could be implemented into the memory management portion of the SPE in the RTOS:
1) Each SPE's task footprint would be made small enough to fit into the 256K LS. Task would be queued in a shared virtual task pipe and fed into the SPE based on either first-come-first-served basis, round-robin or priority scheduling. Any any rate, there would be frequent memory swap accomodated by the PPE MMU.
2) Each SPE would be assigned its own dedicated virtual task pipe and fed into the SPE based on either first-come-first-served basis, round-robin or priority scheduling. Memory swap is accomodated by the PPE MMU.
3) There aren't enough task to load all 7 SPEs and the redundant SPE(s) could be programmed to power the PS3 grill as required. (*yum...)
*
IIRC... the only reason the "redundant" SPE is there is to increase yields. The Cell is a pretty big chip, so it's very likely that there will be some imperfections in many of the chips. Since the SPEs take up most of the space, it's likely that a fault is on one of the SPEs. In that case, they can just disable the SPE and still get a useable chip out of it. All chips that have fully functional SPEs will also have one disabled to maintain consistency. It's the same thing with the XB360 GPU. There are more than 48 ALUs but the faulty ones are disabled to increase yields. I think a lot of modern chips have some sort of redundancy for this purpose.
silkworm
post Jun 16 2005, 02:14 PM

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QUOTE(ray_ @ Jun 16 2005, 01:17 PM)
Actually, I would anticipate a few scenarios that could be implemented into the memory management portion of the SPE in the RTOS:
1) Each SPE's task footprint would be made small enough to fit into the 256K LS. Task would be queued in a shared virtual task pipe and fed into the SPE based on either first-come-first-served basis, round-robin or priority scheduling. Any any rate, there would be frequent memory swap accomodated by the PPE MMU.
2) Each SPE would be assigned its own dedicated virtual task pipe and fed into the SPE based on either first-come-first-served basis, round-robin or priority scheduling. Memory swap is accomodated by the PPE MMU.
3) There aren't enough task to load all 7 SPEs and the redundant SPE(s) could be programmed to power the PS3 grill as required. (*yum...)
*
We can have a peek at the Linux "model" of programming the SPEs in these kernel patches released a couple of months ago. SPEs exist as "files" in the filesystem and that's how program code and data are transferred onto it. The SPEs are idle until a DMA "kick" command is sent to it, after which it looks like it's controlled by the standard POSIX threading API. At least, that's what I've managed to glean from the raw patch data. I'd need to actually patch the full kernel source to see the context of some parts, like the interrupt controller and the memory management unit.

One might also gain insight on the programming model of Cell from the archived presentation/webcast linked from Power.org, from the Barcelona Power conference held last week. I haven't had a chance to view it yet and the webcast isn't downloadable for offline viewing. sad.gif

QUOTE(ikanayam @ Jun 16 2005, 01:27 PM)
IIRC... the only reason the "redundant" SPE is there is to increase yields. The Cell is a pretty big chip, so it's very likely that there will be some imperfections in many of the chips. Since the SPEs take up most of the space, it's likely that a fault is on one of the SPEs. In that case, they can just disable the SPE and still get a useable chip out of it. All chips that have fully functional SPEs will also have one disabled to maintain consistency. It's the same thing with the XB360 GPU. There are more than 48 ALUs but the faulty ones are disabled to increase yields. I think a lot of modern chips have some sort of redundancy for this purpose.
*
Right-o, its all a matter of statistics. Right now fabs are using 300mm diameter wafers, which gives 70,695mm². The Cell processor, weighs in at 235mm². Divide and you get about 300 dies, take away another 20% or so because you're fitting rectangles into a circle, and that leaves you with about 240 dies per wafer. The SPEs cover around 2/3 or 66% of a single Cell die, so that gives a higher chance that defects would form on a SPE. On new processes, the initial yield is usually below 50%. By making one SPE redundant, they may increase the yield up to 60-70%, which is important if they want to hit the volumes that they expect for PS3.

An SPE may be deactivated by firmware, by putting it in a power saving state, or by modifying the metal layers thereby cutting off the power to it on the IC level. If the first option is used, we might see something like what PC overclockers have been doing for a while now; tweaking firmware to unlock deactivated hardware. But that might be pointless because all PS3 software would be targetted for only 7 SPEs and the reactivated one wouldn't be used anyway.
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post Jun 16 2005, 02:41 PM

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Sorry to bug in and makes me look like a total noob....I can't find a better thread to post my stuff so i gona kacau this discussion for awhile..

Japanese developers discuss, and dis, the next-gen consoles
Top game creators from Japan share their opinions on the PlayStation 3, Revolution, and Xbox 360.

QUOTE
Yuji Naka, Sonic the Hedgehog series creator at Sega

PlayStation 3 - "I am very interested in its high-quality graphics capabilities. It's equipped with a graphics chip that's twice as powerful as the high-end [graphics card] for the PC, which allows it to make realistic expressions that haven't been possible before."

Revolution - "I look forward to the 'new kind of fun' that's unique to Nintendo, and I expect that there will be a lot of surprises, such as the unannounced controller. It's also great that we'll be able to play Famicom and other games via download. I hope Sega games will be playable as well." [Note: A number of Sega titles have been released for Nintendo consoles by Sunsoft.]

Xbox 360 - "[Microsoft has] used its knowledge from Xbox Live to evolve their network, making its services and controls even more convenient for the user, which I think is a very attractive point."

Keisuke Kikuchi, Kagero II and Fatal Frame series producer at Tecmo

PlayStation 3 - "It has a very attractive high machine spec. It may be difficult to design a system that can balance out the use of its power, but it should be worth the effort. It should be fun to make games that tend to require high-quality graphics, such as horse-racing games and horror games."

Revolution - "It's difficult to comment on it since there's been very little information, but I'm looking forward to the controller that's yet to be announced."

Xbox 360 - "It's a well-balanced machine. Its CPU, graphics, memory, network capability, and convenience of hardware control are at a high level. I would like to make a game that takes advantage of its online connection."

Masanori Takeuchi, Otogi series producer at From Software

PlayStation 3 - "To be honest, it's still full of unknown factors, and it's difficult to comment on. In my own opinion, it doesn't seem like hardware that will make games more fun. It's being called a 'supercomputer', so I guess it's like a set top box which functions like a PC. My impression [of the console] is like, 'It can also play games, which is good.'"

Revolution - "It's like a console that old-time gamers can drool over. It still has some mysteries, but it's not too difficult to imagine what the machine can do, so there should be people that are clearly looking forward to purchasing it. Its capabilities such as the function to play with the DS via Wi-Fi connection might change the way of gaming, and it's interesting."

Xbox 360 - "It seems like a standard evolvement from the current generation [of consoles]. Whether that's good or bad would depend on the opinion of different people. But it's obvious that the console is meant for heavy users. I believe it's also a console that publishers can use their accumulated knowledge the most [out of the next-generation machines]. It's the best hardware if you have a good fund and you don't want to take risks in development."

Noritaka Funamizu, former Capcom producer and current executive director of Craft & Meister

PlayStation 3 - "It's hardware with the utmost power. I believe it can realize new expressions in both graphics and music, in ways that haven't been possible until now."

Revolution - "There hasn't been much information released about it yet. But I'm looking forward to it as a machine that will feature a distinct kind of fun, different from the direction that the PlayStation 3 and Xbox 360 are headed."

Xbox 360 - "It has a high [hardware] capability, but it's also strong in terms of network and it's also a major console in the American market. So I am planning on title[s] with those aspects kept in consideration."

Yoshiki Okamoto, former Capcom executive and current representative of Game Republic

Xbox 360 - "When considering the titles by Q entertainment's Mizuguchi-san, Mistwalker's Sakaguchi-san, and other games that will be announced in the future, the Xbox 360 should have enough firepower to fight in the next-generation console war. The independent creators such as myself are like the front line that's meant to cut through [the enemies] and start off a good pace, with an army [of publishers] following right behind us."

Kou Shibusawa, producer at Koei

PlayStation 3 - "We showed a trailer of Ni-oh at E3 in May. This game will take full advantage of the extreme hardware spec of the PlayStation 3. Being able to show movie-quality CG in real-time raises our creativeness, and it stimulates our heart as creators. We hope our challenge on new product[s] that will stun our users."

Revolution - "It seems to be going in a different direction from the other two consoles, and it's trying to develop its own unique market. Being able to play old games from the Famicom era should be enticing to the gaming generation, and as a creator, I look forward to playing my games that I have a special fondness for. Aside from having good graphics, the Revolution's uniqueness and concentration towards gameplay should make it a product that's good towards all ages."

Xbox 360 - "Aside from the machine specs, I see great potential in its network capabilities and connectivity with PCs, which is Microsoft's territory. When thinking about the future of online games, I feel the urge to create a new product that takes advantage of [Xbox Live]. Since the Xbox 360 is coming out first, I am very interested in looking at how it will affect the market."

Seems like next gen console, each has evolve into something unique...you like nasi lemak, chow kue teow or roti canai? Damn, i should stop reading hideo kojima's interview...

Okay..you guys carry on..
ray_
post Jun 16 2005, 03:19 PM

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QUOTE(silkworm @ Jun 16 2005, 02:14 PM)
We can have a peek at the Linux "model" of programming the SPEs in these kernel patches released a couple of months ago. SPEs exist as "files" in the filesystem and that's how program code and data are transferred onto it. The SPEs are idle until a DMA "kick" command is sent to it, after which it looks like it's controlled by the standard POSIX threading API. At least, that's what I've managed to glean from the raw patch data. I'd need to actually patch the full kernel source to see the context of some parts, like the interrupt controller and the memory management unit.

One might also gain insight on the programming model of Cell from the archived presentation/webcast linked from Power.org, from the Barcelona Power conference held last week. I haven't had a chance to view it yet and the webcast isn't downloadable for offline viewing. sad.gif
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Where do you get all these links anyway? (* shake fist)

Looks like linux folks are implementing method 2). But IMHO, 1) would spread the processing load more evenly across all SPEs.

"We will need our own address space operations as soon as we allow the SPU context to be scheduled away from the physical SPU into page cache."

PPE MMU will be segmenting the memory into pages thus one could swap a code or data page into the LS as one deem necessary. Page granularity in the context of the PPE MMU should be adjustable. Given the small size of the LS, it would be more useful to set a larger PPE MMU page size to load the task to its entirety. But having a smaller page size would give the programmer the flexibility to apply data protection mechanism of the MMU at a smaller scale.

It would be interesting to see how Sony plans to implement its Level 1 kernel.

EDIT: It would be nice if these segmented swap memory has some scheduling capability built in (hence a programming paradigm) where in the case of linux, scheduling information can be embedded into the mem file section headers. An a dispatcher could be implemented to arbitrate between task.

This post has been edited by ray_: Jun 16 2005, 03:29 PM
ray_
post Jun 16 2005, 04:21 PM

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From: Wallowing in my Pool of Ignorance (splat..splat..)
From fa.linux.kernel:
"spu_run suspends the current thread from the host CPU and transfers the flow of execution to the SPU.


Wait, I thought the operation of the PPE is independent to the SPE. Why is there a need to stall the PPE to service the SPE? They should both run independently.

This post has been edited by ray_: Jun 16 2005, 04:25 PM
silkworm
post Jun 16 2005, 04:39 PM

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Take it easy, the host thread is stalled, not the entire PPE. The SPU/SPE is going to be encapsulated into a Pthread, as you will see in the "bpathread.c" module.

Edit - oops, in my haste, I grabbed the google groups link off my browser history list, and apparently that thread didn't have the whole set of patches. No worries, the complete set of 8 patch files are available on the linux kernel mailing list archive, run a search for "ppc64 bpa" should get you the right hits.

This post has been edited by silkworm: Jun 16 2005, 05:12 PM
ray_
post Jun 16 2005, 05:17 PM

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QUOTE(silkworm @ Jun 16 2005, 04:39 PM)
Take it easy, the host thread is stalled, not the entire PPE. The SPU/SPE is going to be encapsulated into a Pthread, as you will see in the "bpathread.c" module.
*
Ah....I remember now. The kernel scheduling is centralized on the PPE because the SPE does not have a resident RTOS.

If the SPE were to have a resident RTOS, things would be very different.




ikanayam
post Jun 17 2005, 01:08 AM

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QUOTE(silkworm @ Jun 16 2005, 01:14 AM)
An SPE may be deactivated by firmware, by putting it in a power saving state, or by modifying the metal layers thereby cutting off the power to it on the IC level. If the first option is used, we might see something like what PC overclockers have been doing for a while now; tweaking firmware to unlock deactivated hardware. But that might be pointless because all PS3 software would be targetted for only 7 SPEs and the reactivated one wouldn't be used anyway.
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I'm sure they will cut it off on the hardware level to make sure meddlers don't mess around with it tongue.gif
and also because cutting off power on the IC level would be a bit better in terms of saving energy than a low power state.
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post Jun 17 2005, 04:23 PM

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the cell just seems so messy to me
SUSMatrix
post Jun 20 2005, 04:21 PM

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More tongue stabbing from Ken Kutagari (who has recently went a bit wild/mad) at MS:

In the area of backwards compatibility, Kutaragi finds some time to take shots at the competition (he also does this quite a bit in part 1 of the interview). "With the Xbox next generation coming in November of this year, the current Xbox will become last generation. With that, the Xbox will kill itself. The only way to save it is to have 100% backwards compatibility from the first day. However, it seems that [Microsoft] cannot make that commitment -- on a technology level, it's difficult."


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post Jun 21 2005, 06:18 PM

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Here's some interesting info... Apparently, the PS3 is smaller than the Xbox360 according to this.

Courtesy of Evil Avatar

That image of it being a barbeque grill is still with me tongue.gif
ccb
post Jun 21 2005, 07:02 PM

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lol,i want a steak grill not barbeque grill smile.gif
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post Jun 22 2005, 09:19 AM

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QUOTE(ccb @ Jun 21 2005, 07:02 PM)
lol,i want a steak grill not barbeque grill smile.gif
*
Make sure call me to the party when you guys are grilling the lamb...LOL.

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