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 Intel proposes dropping 16 and 32-bit support, Start to develop pure 64bit apps ?

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TSflashang
post Jul 19 2023, 11:15 AM

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QUOTE(narf03 @ Jul 19 2023, 01:19 AM)
each bit extra is twice the capacity, i wonder when we will move towards 128 bit.
*
For register, currently there are CPU up to 512 bit.

For memory, may be after 64 bit addressing is no enough...
Which is ...

64 bit = 18,446,744,073,709,551,616 (16 Exabytes).
1 EB = 1'024 PB = 1'048'576 TB.

smile.gif



This post has been edited by flashang: Jul 19 2023, 11:16 AM
MatQuasar
post Jul 19 2023, 10:22 PM

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QUOTE(flashang @ Jul 19 2023, 11:15 AM)
For memory, may be after 64 bit addressing is no enough...
*
Last time I encounter 64-bit address is not all accessible, only 40-bit address, and need some tweaks to access all 64-bit memory.... doh.gif

Then when doing bootloader also I encounter A20 line, or else cannot access full width of memory address (not sure how many bits).....
That's when I start pening pening kepala, give up studying the width of bus, memory address... rclxub.gif rclxub.gif
TSflashang
post Jul 19 2023, 11:28 PM

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QUOTE(MatQuasar @ Jul 19 2023, 10:22 PM)
Last time I encounter 64-bit address is not all accessible, only 40-bit address, and need some tweaks to access all 64-bit memory....   doh.gif

Then when doing bootloader also I encounter A20 line, or else cannot access full width of memory address (not sure how many bits).....
That's when I start pening pening kepala, give up studying the width of bus, memory address...   rclxub.gif   rclxub.gif
*
A20 is designed to be default off, for compatible with older system (8086 / 8088 / 80168).

40 bit address can handle up to 1 TB (some system is 48 bit up to 256 TB),
We're not going to see a system which needs more than that so soon.

So hardware manufacturer (CPU & motherboard) can cut cost for not design such large bus.

Ref :
A20 line - Wikipedia
https://en.wikipedia.org/wiki/A20_line

P/S : For more info about memory addressing,
you may also check how those old 4 / 8 bit CPU and bus designed.

smile.gif



This post has been edited by flashang: Jul 19 2023, 11:30 PM
MatQuasar
post Jul 25 2023, 08:10 PM

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APX!

https://www.intel.com/content/www/us/en/dev...nsions-apx.html

QUOTE
Intel® architecture powers datacenters and personal computers around the world. Since its introduction by Intel® in 1978, the architecture has continuously evolved to take advantage of emerging workloads and the relentless pace of Moore’s law. The original instruction set defined only eight 16-bit general-purpose registers, which over the years were doubled in number and quadrupled in size. A large set of vector registers was added, and most recently Intel® AMX introduced two-dimensional matrix registers, providing a big jump in AI performance.1

Today, we are introducing the next major step in the evolution of Intel® architecture. Intel® Advanced Performance Extensions (Intel® APX) expands the entire x86 instruction set with access to more registers and adds various new features that improve general-purpose performance. The extensions are designed to provide efficient performance gains across a variety of workloads – without significantly increasing silicon area or power consumption of the core.

Intel® APX doubles the number of general-purpose registers (GPRs) from 16 to 32. This allows the compiler to keep more values in registers; as a result, APX-compiled code contains 10% fewer loads and more than 20% fewer stores than the same code compiled for an Intel® 64 baseline.2 Register accesses are not only faster, but they also consume significantly less dynamic power than complex load and store operations
This post has been edited by MatQuasar: Jul 25 2023, 08:13 PM
acbc
post Jul 25 2023, 08:11 PM

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Should have done this decades ago.

People with 16 or 32 bit apps won't upgrade the hardware anyway. Many still keep running until it breaks down.
MatQuasar
post Jul 25 2023, 08:12 PM

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QUOTE(narf03 @ Jul 19 2023, 01:19 AM)
each bit extra is twice the capacity, i wonder when we will move towards 128 bit.
*
As @flashang said, now we have 512-bit vector registers, although general purpose registers are only 64-bit.
TSflashang
post Jul 25 2023, 11:30 PM

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QUOTE(MatQuasar @ Jul 25 2023, 08:10 PM)
To use a new instruction set,
you may need to "update" compiler, some libraries,
recompile whole system and do a lot of stress test.

Unless it have huge improvement, otherwise just use old system.

hmm.gif


eclectice
post Aug 1 2023, 02:49 PM

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Those Windows-based 32-bit test bench PCs in the manufacturing facility would undoubtedly suffer if their codes continue to employ 32-bit vendor device driver libraries; some are legacy driver codes that have not been changed to 64-bit.
TSflashang
post Aug 1 2023, 04:07 PM

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QUOTE(eclectice @ Aug 1 2023, 02:49 PM)
Those Windows-based 32-bit test bench PCs in the manufacturing facility would undoubtedly suffer if their codes continue to employ 32-bit vendor device driver libraries; some are legacy driver codes that have not been changed to 64-bit.
*
Some machine need special software to operate,
and the software may only run on XP.

Unless you have budget to change the whole system,
or something damage cannot repair / no replacement,
force you change new set.

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MatQuasar
post Sep 4 2023, 09:33 PM

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QUOTE(flashang @ Jul 19 2023, 11:28 PM)
40 bit address can handle up to 1 TB (some system is 48 bit up to 256 TB), 
smile.gif
*
Thank you for inspiring me, I took note of the following:

I just aware that although PE32+ uses QWORD runtime address in memory, but in reality it will never use up all the high order DWORD, because even 40-bit address is enough for 1TB RAM.

Image base in PE32+ may starts with 0x0000 0001 xxxx xxxx

(The QWORD address above is 36-bit)
MatQuasar
post Sep 4 2023, 09:34 PM

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QUOTE(flashang @ Jul 19 2023, 11:28 PM)
40 bit address can handle up to 1 TB (some system is 48 bit up to 256 TB), 
smile.gif
*
Thank you for inspiring me, I took note of the following:

I just aware that although PE32+ uses QWORD runtime address in memory, but in reality it will never use up all the high order DWORD, because even 40-bit address is enough for 1TB RAM.

Image base in PE32+ may starts with 0x0000 0001 xxxx xxxx

(The QWORD address above is 36-bit)

 

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