duo core tri core quad core ... there are no differences if the applications u are running are not optimised to take full advantage of them

When you can't make 4 make 3 and call it a feature. 

But it'll be interesting to see how AMD markets this one: duals are cheap and quads are just slightly costlier; any tri-core would have to fit in the small gap in between. AMD already has their hands full with the fallout from Barcelona's muted launch and lukewarm market response + getting Phenom out. More SKUs = more work = more issues.

When you can't make 4 make 3 and call it a feature. 

But it'll be interesting to see how AMD markets this one: duals are cheap and quads are just slightly costlier; any tri-core would have to fit in the small gap in between. AMD already has their hands full with the fallout from Barcelona's muted launch and lukewarm market response + getting Phenom out. More SKUs = more work = more issues.

Lolz, Isn't it obvious AMD trying to clear their old stocks before Phenoms coming??

Indeed, marketing will be interesting. As far as intel is concerned, there seems to be no gap between quad and dual cores, pricing wise. The Q6600 is already really cheap for a quad core.
This IS a phenom.

Speaking of bad yield, what if the quad core have two defective cores? Can they still make use of the other 2 cores?

hmmm~ i think triple core is more efficient than double dual core (current intel quad)...

That said, I'd like to see Intel responding with an even cheaper quaddie. And also cut the darn platform price too.

We dun really need this IMHO. A slighty cheaper quad core proc in a month or  so will do.

There is already a cheaper quaddie than the Q6600. Do you know that the Xeon X3210 is actually using LGA775 package?

Check it out: Neoseeker: X3210 Xeon Core 2 Quad: Overclocking Monster in Sheep's Clothing! 

Sooner or later, the quad prices will come down even further with Phenom and Penryn on the horizon

There is already a cheaper quaddie than the Q6600. Do you know that the Xeon X3210 is actually using LGA775 package?

Check it out: Neoseeker: X3210 Xeon Core 2 Quad: Overclocking Monster in Sheep's Clothing! 

Sooner or later, the quad prices will come down even further with Phenom and Penryn on the horizon

It is a weird product surely, but AMD probably needs it at this point. Even a single cutdown core should help quite a bit with yield, unless it is really bad. Intel is likely to slash their quad core prices even lower if needed, so AMD may have to position this vs the dual cores in terms of price.

Hehe,why you say so?Any documents or benchmark from internal?

On NCIX it's ~950 ringgits, that's precisely where the cheapest 6600 batches retail for now.

The X3 isn't targeting the C2Q market- it's locking on to the E4300-6850s we buy today.
(Note: 3 cores > 2 cores in promotion, OEMs might actually snatch these chips faster than the retail channel would)

Hmmmm.... Did you check Lowyat's own price lists? According to our retail price here its about RM899 only!  (e.g Compuzone price list)

Ahem! The E6850 and Q6600 are about the same price. If the tri-core is targetting low end to mid range dual core segment, that makes sense... However the manufacturing cost of the "tri-core" is much higher than dual cores due to the die size (which is actually quad core die size). My guess is AMD is trying to get some leverage in this part of the market, rather than reducing them to just "dual cores".... I can hear the words "Buy 2 Get 1 Free!" 

On the yields issues, here's an interesting find (from AMD's own slides), see the "Defect densities below 0.5mm^2"....



And according to this http://smithsonianchips.si.edu/ice/cd/CEICM/SECTION3.pdf ..theoretically Barcelona's huge 283mm^2 dies have only less than 30% yields. The other 70% are considered defective and that's quite a big amount, definitely big enough for AMD to start the 3-core product line.

1- AMD should be taking the Intel Core approach to all its CPUs- all the same model, bin and cut. This would equate to much higher yields than 30% even on the fully functional QC units on the long term, and hidden cost savings in getting a unified chip to all SKUs.

Once 65 matures to AMD's sweet spot (their later steppings are quite good, evidenced by their 90 work) they won't have that much of a problem competing.

2- It should improve by time- getting unified (I don't know if Kuma is even native dual or cut-down quad) might also get clocks to competitive speeds, even in dual/tri cut-down scenarios. If AMD can get production of 3.2Gigas (B2 Max, B3 is currently unknown) before Q2 ends, kudos to 'em.

3- C2Qs are only made cheaper nowadays because Core manufacturing is already rather mature at the 65 level, plus the retooling to 45 CMOS they would have no incentive to price that high for even the base chip (Note the Q6700 is still there for margin suckers lol)

ps: Shanghai could make it considerably smaller (<200?), if they get hi-k dielectrics they'd be on even ground with Penryn clock wise. (Yet the fact that AMD's collab with IBM on SiGe on 65 might indicate that they're delaying it.)

Mario Rivas once said "If I could do something different, I wish we would have immediately done a MCM - two dual cores and call it a quad-core," (see The Register: AMD praying 'Barcelona' makes up for four-core mistake)

Have you wondered why AMD's fastest dual cores (like the 3.2GHz X2 6400+) are still on 90nm, and the highest clocked 65nm dual core is 2.6Ghz only? AMD hasn't hit the 65nm sweetspot yet and still have a long long way to go.

So far we have only seen 2GHz, even the announced release is 2GHz. And the 2.5GHz Anandtech had seems to be overclocked. So the 3.2GHz figure still looks a long way far off. 2.5Ghz to 2.6GHz looks more likely, IF they can reach "maturity" like their dual cores. That's a big "IF"...

Intel's 65nm matured very quickly, as did Intel's 45nm (as seen from the 3.33GHz Penryn showing at Beijing IDF).  

IMHO I think AMD should abandon SOI, just look at all the delays and "technical glitches" (as quoted by Hector Ruiz recently). Intel once warned AMD about going 65nm on SOI (e.g. "floating body effects"), and if I'm not mistaken AMD's "65nm" isn't exactly ideal shrink.

So far we have not seen any working 45nm prototypes from either AMD or IBM, just announcements, PR statements and wafer fashion show. Sorry for being harsh, I am a "show me the beef" guy.

30% theoratically- but there are a lot of 'buts' I think.
1- AMD should be taking the Intel Core approach to all its CPUs- all the same model, bin and cut. This would equate to much higher yields than 30% even on the fully functional QC units on the long term, and hidden cost savings in getting a unified chip to all SKUs. Once 65 matures to AMD's sweet spot (their later steppings are quite good, evidenced by their 90 work) they won't have that much of a problem competing.

2- It should improve by time- getting unified (I don't know if Kuma is even native dual or cut-down quad) might also get clocks to competitive speeds, even in dual/tri cut-down scenarios. If AMD can get production of 3.2Gigas (B2 Max, B3 is currently unknown) before Q2 ends, kudos to 'em.

3- C2Qs are only made cheaper nowadays because Core manufacturing is already rather mature at the 65 level, plus the retooling to 45 CMOS they would have no incentive to price that high for even the base chip (Note the Q6700 is still there for margin suckers lol)
ps: Shanghai could make it considerably smaller (<200?), if they get hi-k dielectrics they'd be on even ground with Penryn clock wise. (Yet the fact that AMD's collab with IBM on SiGe on 65 might indicate that they're delaying it.)

Mario Rivas once said "If I could do something different, I wish we would have immediately done a MCM - two dual cores and call it a quad-core," (see The Register: AMD praying 'Barcelona' makes up for four-core mistake)

Have you wondered why AMD's fastest dual cores (like the 3.2GHz X2 6400+) are still on 90nm, and the highest clocked 65nm dual core is 2.6Ghz only? AMD hasn't hit the 65nm sweetspot yet and still have a long long way to go.

So far we have only seen 2GHz, even the announced release is 2GHz. And the 2.5GHz Anandtech had seems to be overclocked. So the 3.2GHz figure still looks a long way far off. 2.5Ghz to 2.6GHz looks more likely, IF they can reach "maturity" like their dual cores. That's a big "IF"...

Intel's 65nm matured very quickly, as did Intel's 45nm (as seen from the 3.33GHz Penryn showing at Beijing IDF).  

IMHO I think AMD should abandon SOI, just look at all the delays and "technical glitches" (as quoted by Hector Ruiz recently). Intel once warned AMD about going 65nm on SOI (e.g. "floating body effects"), and if I'm not mistaken AMD's "65nm" isn't exactly ideal shrink.

So far we have not seen any working 45nm prototypes from either AMD or IBM, just announcements, PR statements and wafer fashion show. Sorry for being harsh, I am a "show me the beef" guy.

AMD did NOT tape out Brisbane >2.6 (though OCs to 3+Ghz was quite feasible) because it's useless then- Intel counters with higher clocks/price drop, your ASPs dive, your next chip is held on an even higher clock bar to compete with. They went for IPC first, and IMO the only feasible solution.

hmmm interesting news you have there

arjuna_mfma

who knows in the old days AMD could win Intel but lately it seems they are fighting an uphill battle

Seems to me like the problem was more of leakage at higher voltages/clocks. That's why they could not get the clocks up too high on the 65nm shrink. It would have worked (as evidenced by 3+ghz overclocks), but exceeded the thermal budgets.

Ottelini replies Mike Magree question about tri core approach and the Otteini said that We(Intel) try to make all of our cores to work.

AMD's 65nm transition looks to be like intel's 90nm transition. It does seem to have caused them quite a bit of problems. Leakage seems to be a big pproblem.

89W TDP 3.2 could be possible (strict binning like 90 F3 does)

but in the end, what's the motif for launching a product at the top bin when it should be costly and not even win over the buyers of Core 2s (people spending that much tend to OC, and compared to a 65W C2D it doesn't bode well to OEMs)

I have a strong feeling that this could go up to say, 2.6 in B2 and still be 65W (X4 will be 89).

Sorry Ortellini said otherwise...  No tri-cores from Intel. 

I think possibly due to the gate thickness, as shrink goes down the effective thickness reduced further and probably reached a point where its insulation properties becomes almost void and leakage starts. Using SOI seems to have accelerated this...

Tell me what is the TDP of the 2Ghz Barcelona? Its 95W, thus 89W at 3.2 does not look remotely possible.

Pure speculations.... I'm sure AMD would like to launch the products at top bin... to get back the performance crown, revitalize sales and boost ASPs. For the moment being they have to sort out their "technical glitches".... 

For duals its possible, BUT not for the quads even at 2.6Ghz. 

Well now they're marketing ACP instead of TDP. If you can't change the physics, change the game

SOI and gate oxide thickness (i assume this is what you really mean) are orthogonal. Gate oxide thickness is no longer reduced these days. It's already ~1nm thick, they can't really cut it down much more without bad electron tunneling effects. And it is a design choice, it's not like the gate oxide thickness was reduced as an uncontrollable consequence of newer process technology.

Issues with SOI: Feeling the heat

However, SOI does face some other issues that still need to be addressed. Heat dissipation is one problem. Although SOI technology can curb leakage current, the heat dissipation efficiency of the insulated substrate is not as good as a silicon substrate. It is a major problem for today's chips, as high-end processors' heat output reach as high as 300W per square centimeter. The dissipation rate of common silicon substrates are 120-150W/m-K, but the heat dissipation rate for a SiO2 substrate is far lower at 30-59W/m-K. Obviously, the insulator not only prevents current from leaking, but also prevents heat from escaping.

As SOI has an extra insulation layer between the substrate and the transistor to reduce leakage current, it necessarily adds extra material and process costs to production. Some estimates indicate that SOI is 10-15% more expensive to produce than ordinary chips. For chips that are under fierce pricing pressure, or those that lay heavy emphasis on cost effectiveness, SOI does not seem an attractive option.

With the processes shrinking, more and more transistors are squeezed into each unit. And as each transistor has its own current, the total current for each unit therefore increases. But as the circuits become finer, the working voltage has to be lowered. But lower working voltage means that signals are more difficult to recognize. The finer circuits also result in poorer insulation of the gate, causing poorer signal reception. With transistors closer to one another, it is easier to create noise interference. These are some of the common issues the semiconductor industry has to address amid shrinking processes.

Apart from these issues, the radiation permeating the Earth, including solar wind from space, can cause instant flows of electrons inside silicon chips, creating noise interference. The SiO2 used in SOI, however, is prone to ionization, and therefore radiation can trigger currents that create noise

x264 support multicore. so u multicore skeptics. go away

Sorry Ortellini said otherwise...  No tri-cores from Intel. 

I think possibly due to the gate thickness, as shrink goes down the effective thickness reduced further and probably reached a point where its insulation properties becomes almost void and leakage starts. Using SOI seems to have accelerated this...

Tell me what is the TDP of the 2Ghz Barcelona? Its 95W, thus 89W at 3.2 does not look remotely possible.

Pure speculations.... I'm sure AMD would like to launch the products at top bin... to get back the performance crown, revitalize sales and boost ASPs. For the moment being they have to sort out their "technical glitches".... 

For duals its possible, BUT not for the quads even at 2.6Ghz. 

AMD now playing the Intel game.

Just FYI, I was reading that from here: Digitimes: The development of SOI technology....

It's 95W @ B1. B2 is the "miracle" stepping (no, I didn't dub that ) that's why Phenom FXes and real production Barcelonas (not early revs) start from B2.

Currently highest known B2 speeds are 3.2/3.4 so it is possible, given some maturation time and newer spins.

I was mentioning X3s. Tris could fit in 65W ACP (lol) with B2, but I think the breakneck speed will be 2.6 where it'll be classified 90 even if it uses a little bit more.

Anand's "B2"s were B1s. Every site pre Barcelona launch were given B1s (not BAs, B1s) With overvolt of course, you'd get 2.5Ghz out of those, but in general BA/B1 can't scale nicely above 2Ghz.

But why stop at BA or B1.  The 2.5 GHz samples featured on AnandTech's second article are of the newest roadmapped spin; revision B2.

You've seen all the Phenoms at 3Ghz. Fudo had it at 3.2 and 3.4 as the max speeds the B2s would go (forgot if voltmods were applied or not)- these should be the AM2+ chips without coherent HTT, for Opterons I'll give 2.6 a rather high bin.

According to some internal information Barcelona / Phenom X4 Quad core can hit 3.24 GHz. This is the top speed of the B2 revision of the core.

We already reported that AMD can hit 3.0 GHz at 1.38V and a TDP (Thermal Design Power) of a still acceptable 120W.

By normal air cool, the AMD Phenom X4 can go beyond the 3GHz mark by overclocking. Although this can be done, there are some stability issues at such high speed.

Currently, there aren't any options to turn off one or two of the cores. Running it in single channel memory helps to stabilise it.

For my "speculations", I give you 2 letters: G0.

Hmmm... That's not what Kristopher Kubicki said at DailyTech: Stumbling in the Aisles: "Barcelona" Thoughts

Do you believe everything from the one who made up the "reverse hyperthreading"? Well, that's ex-INQuirer FUDo!

And you still have not provided the link or evidence yet? If you are referring to Fudzilla: Phenom X4 can hit 3.24 GHzLike I said before, you pulled this one from thin air again. Where are the "3.3/3.4"? Also FUDo never "had it"... Meanwhile this contradicts Anand's 2.5Ghz B2 which needed 1.52V.

Now this one is interesting (since it wasn't from Mr. FUDo): OCWORKBENCH PC News Headlines: AMD Phenom X4 can do 3GHz and above

If you are referring to Q6600 G0 stepping, those are 95W TDP (Intel's) at 2.4GHz. To make matters more interesting the Q6600 had total of 8MB L2 cache, while Barcelona 2GHz has total of 4MB (L2+L3) only. Usually more cache = higher power consumption. Interesting, eh?

You really didn't get it, didn't ya?

B3 -> G0. What exactly happened to the thermals... I dunno.

Truth is, you're basing the whole future of a chip on a preproduction stepping. If you need to voltmod to 2.5, that's pretty bad and reeks of B1 (when B2 can run off air, you'd ROFL at such a big voltmod for 2.5 if it were)

Barcey B1 2Ghz doesn't go up to 90. Server thermals are very airy and you know that too.

What is AMD about to release on September 25, 2007?

So explain what your hint at G0 was about. We are interested to see what exactly you are thinking.
And you are basing the whole future of a chip on rumors relating to a new stepping. I'm not sure your arguments are more credible.

Usually more cache = higher power consumption

Venom sounds like Phenom...
Ah he's going to doublespeak on the whole B1/BA/B2 stepping again...
Nope cache is pretty low power compared to other parts of the CPU.

B3 -> G0. What exactly happened to the thermals... I dunno.

Truth is, you're basing the whole future of a chip on a preproduction stepping. If you need to voltmod to 2.5, that's pretty bad and reeks of B1 (when B2 can run off air, you'd ROFL at such a big voltmod for 2.5 if it were)

So explain what your hint at G0 was about. We are interested to see what exactly you are thinking.
And you are basing the whole future of a chip on rumors relating to a new stepping. I'm not sure your arguments are more credible.

Ah he's going to doublespeak on the whole B1/BA/B2 stepping again...

Just by a stepping Q6600 went from 105 to 95 (consumer markets normally don't use tiered TDPs as they don't need that buffered luxury that much) and I guess it's pretty tight around that too- older QXs, I don't know their stepping revs, but 130W (even a "loose" 110W) is a lot.

We only have Opteron TDPs. AMD could pull an Intel, get the consumer tri-cores at 75W or a non-standard rating just to make it look lower/closer to the real TDP it has (definitely more than 65W in high clocks, they can bin, squeeze BE chips, but that's out of the matter).

Iit's not like AMD's faultless too. They should have prioritized Barcelona more than Brisbane for 65 (it was nary a stopgap) but in the end, OEMs talk louder than anyone, and they do like cooler chips.

Let's see how they will name 6 cores

Okay, this is just a hypotethical question, and a bit off topic. If (and it's a big "if") they double the triple core and make a 6 core processor, will it be called a "sex core"?

haha, sex-core --> one of the cores are dedicated for xxx processing, lol. btw, I have reliable sources that future generation CPU core doesnt not follow power of 2 (2, 4, 8, 16 etc...) Let's see how they will name 6 cores

Yes, because TDP is tiered for servers. Go above 65 a little bit and boom, you're at 89/90.
Go above 90 (for Xeons), and Kaboom, 125. That's what the highend Penryn Xeon looks like (125W TDP, but a very practical guess should be <100W)

Just by a stepping Q6600 went from 105 to 95 (consumer markets normally don't use tiered TDPs as they don't need that buffered luxury that much) and I guess it's pretty tight around that too- older QXs, I don't know their stepping revs, but 130W (even a "loose" 110W) is a lot.

We only have Opteron TDPs. AMD could pull an Intel, get the consumer tri-cores at 75W or a non-standard rating just to make it look lower/closer to the real TDP it has (definitely more than 65W in high clocks, they can bin, squeeze BE chips, but that's out of the matter).
Iit's not like AMD's faultless too. They should have prioritized Barcelona more than Brisbane for 65 (it was nary a stopgap) but in the end, OEMs talk louder than anyone, and they do like cooler chips.

@Aoshi_88
Sex cores need ultimate protection. Pedal to the metal just ain't gonna work.
Butter?

hardcore & sexy edition

I'm starting to get lost.    

Ah he's going to doublespeak on the whole B1/BA/B2 stepping again...

lex, if the Core 2 Quad didn't have a G0, I'm seriously thinking about your google skills.

AMD might not want to bite what it can't chew. B2 for now is for the AM2+ Phenoms and upcoming newer Opterons 2/8300s. Coming November (earliest) so we have 2 more months to moan.

Me too...   Quoted for reference....

hey... phenoms wont use am2 socket rite?
should be on am2+????
i want to upgrade my gc,mobo,proc...
so all my cpu suing high end stuff haha

haha, sex-core --> one of the cores are dedicated for xxx processing, lol. btw, I have reliable sources that future generation CPU core doesnt not follow power of 2 (2, 4, 8, 16 etc...) Let's see how they will name 6 cores

I don't think they will come out with 6 cores... Maybe they will jump straight to 8... but anyway, I was shock to when AMD has a 3 cores processor... I am more interested how will they name 5 cores than... but... will there be a 5 cores processor? 

i don think it will use same socket... and i also won say AM2+...

i think it will be optimized for ATI chipset based mobos... so bye bye nForce and the rest...

AM2+ CPU can be slot into AM2 sockets.

However, you will have 2 issues (quite confirmed I think)
1. Lack of HT3.0. This might be instrumental, as how the K10 uses the L3 victim cache and the extra latency, HTT speeds might matter.

2. This one is more crucial- your memory controller speed. For mobos without Split power plane (AM2+) support, your IMC will run *even* more slower than the CPU (it already does in K10, by 100-200Mhz). Might affect performance for all it's worth.
To be honest, the new RD790 mobos should be good and hopefully, also cheap (single card versions FTW). It should be the easiest chipset for AMD overclocking period. (Not like it wasn't easy using ClockGen anyway/ )

When you do MCMs they better be symmetrical.

So on 4-core die, the only other possibility would be sex.