zomg i think i will have to reduce it to 16 bits... they are limiting the pins to 100 pins so a 32 bit design would be a bit too big... >128pins...

Either that or i can cheat and do a 32bit multiplier only... easy to design, layout and pipeline... but then that is so uncool functionality wise.... sigh... decisions decisions....

Circuit theory isnt hard actually, but circuit signal is much tougher, esp the analog part. IMHO, Field theory and electromagnetic is the most troublesome one


haha, 16-bit with 32-bit multiplier seems ok mah. how about 32-bit input, 16-bit output? During the output u can pipeline it, make it 2 clocks

32bit input to 16 bit output would be quite pointless i think... the whole point is to have the accuracy preserved when moving to 32 bits. I'm wondering if i should make a 32bit FP multiplier (been done before but i think i can do them 1 better but still... so uncool ) or a 16bit MAD/FMAC unit. I think the latter is a lot cooler functionality wise. Doing a 32bit MAD/FMAC would be too big for the scope of the project and too time consuming for the layout part i think. I'm not too confident in the abilities of my project partners

Bump for great justice!

So i am going ahead with my 16 bit FMAC. The specs are almost done, and soon verilog work will start in parallel with schematics. Still experimenting with adder designs for my 24 bit adder....

What technique are u going to use for adder?
Will it be a balance of speed and size, or should be as small as possible?

With your current gate library, don't think can have more than CLA2

I'm using a variable length carry select adder, hand tuned specially for my purpose. The objective is be speed. I am still experimenting with some other hybrid adders, so this can still change.

Btw i'm adding a register array to enable thread switching to avoid pipeline stalls. Something like what the R5xx does. But very basic.

I have some hybrid adders built from yr standard gates
If you want I can send u the config and the propagation delay

However, i only has 1 carry select implementation for the speediest adder

(bump for great justice)

IBM kicks Power6 to 6ghz. Pretty amazing if true.
http://www.theregister.co.uk/2006/02/07/ibm_power6_show/

hello guys,

i'm taking dld this semester and my project is to design a circuit for decorating lights using only basic logic gates (yes, i know this is very2 basic). the lights must have 6 blinking sequence.

any opinions from all the gurus here? thanx..

What sequence do the lights have blink in? If you're able to use flip flops, just use a counter and strikeout sequences you don't need with a "don't care"

just custom-made sequences. okay, will try it. thanx empire!!

anyone can recommend me a software that can do transistor timing simulation(other than Orcad PSPICE or AccuSim 2)





p/s: but if u have the AccuSim 2 software, please PM me

2nd year computer engineering student reporting

hm... interesting. just finish reading the whole thread, make me remind the old days in uni. lot of fun, as well as headache!! ok, any registration form, pls??

B.Eng (EES Eng), graduated in 1999, ukm.

currently work in mnc, electronic board/product manufacturing (more in product testing functionality), will be joining new co soon jumping in dev job. (hehe... that's why i have plenty of time this few weeks to really join LYN)

hopes to help, but i have a seriously rusted brain, so can only say things about real application (that i know of), not theory (maybe yes if do some serious revision/reading)!!

This post has been edited by WhatCanIdo: Feb 17 2006, 02:52 PM

just succeeded in making my pulsed latch work

that just sliced register delay by about 50%. No more master slave FFs. pulsed latch ftw!!!!

anybody use transmission gates for specific gate operations(xor, mux etc) ?
just wondering, in transistor schematic simulation, did u all place buffers at the input of the transmission gates to avoid it feedbacking the signal back to the input?

This post has been edited by X10A Freedom: Feb 21 2006, 10:34 PM

I use them a lot for my current project. You need buffering if you are stacking pass transistors to speed up and clean up the signal.

hmm, let's say u form a Xor gate using transmission gates
and if u don't put buffers at the inputs
can u're circuit still run? the simulator at my college is giving me lots of headaches
if i can use transmission gates, it'll greatly reduce my transistor counts

My xor gate uses 6 transistors, with pass transistor logic (including transmission gates). The alternative is to use an xnor and inverter on the output (total 8 transistors). What simulator are you using? I'm using spectre for analog simulations (packaged with Cadence).

Pass logic without proper buffering can cause a lot of slowdowns and problems. You have to experiment to find the best settings.

using Design Architect bar the analogue library(apparently my college can't determine which analogue library we should use, so we have to use the digital nmos/pmos library)
the problem is, without putting a buffer at the input, the software apparently assume that the signal at the output of the transmission gate will feedback some signal to the input which in the end render the transmission gate not attractive anymore if i always need to put a buffer just to prevent the signal from feedbacking