All the stuff you mentioned. The overall design and marketability. It's not just one thing.

Free bump + more computer porn! ikanayam's bare naked ALU! Global routing not included (yet)!



About 1000 transistors.

Hehe... not bad... I would never have been able to do something like this.

Just a thought, why don't you restrict the metal layers (except maybe metal 1) to either horizontal only or vertical only.. (eg metal 2 horizontal only, metal 3 vertical only, metal 4 horizontal only, and then do your global routing on metal 5 and metal 6, (still restricted to the horizontal only or vertical only rule. Your layout will look a whole lot neater, but you will use an additional metal layer or 2.. (but you should have 7 layers or so to play with right? why not use all of them) Interconnect parasitics will be higher due to the vias... but you should be able to improve on noise and signal integrity. (especially if metal 2 has a ground horizontally routed)

We are only allowed 4 metal layers
I could have made a more compact design if i had a couple more metal layers to play with. Oh well, engineers exist to find solutions within restrictions

I wanted to do the directional layer thing for metal 3 and 4, but then i realized that i could squeeze everything in better by just using the metals the way i thought best. There are some semi directional layers within certain modules, but overall i think it's the best i could do for a size optimization. The final layout will be smaller than that for sure. This is just the initial floorplan. The modules were never optimized for a best fit in the overall design, i just did local size optimizations. However perhaps by good fortune, they seem to fit in pretty well. I would like the final layout to be more squarish though.

Btw it should be obvious that made all the modules except the ugly looking one at the bottom right corner (which was left to my partner). As usual, i will have to redo it (over thanksgiving break)

This post has been edited by ikanayam: Nov 20 2005, 09:25 PM

Complete and (almost) final layout. (but mostly an excuse for a bump )

Dead image link for us here..
we will wait for your uni's host to come back up

CMU... Carnagie Mellon? Wow..... Now we know the difference between a local grad and a foreign grad

Is it still dead? it's working for me. Hell yeah tested it and it works the 1st time One more project to go!!

This also does not show you anything besides the fact that i love doing IC design. It's really not that hard to learn this stuff. The difficulty is in making a good design (small, fast, low power). That will "separate the men from the boys" according to my professor

results:



wondering why i get so many 'spikes'.. anybody can help me? thanx

The spikes are glitches due to timing...
just take an NAND gate for instance... if we change the input from 01 to 10 the result should be a constant 1 right? but if the input may change from 01->11->10 (the second bit changed a few pico seconds after the first bit, then you will end up with 1->0(glitch)->1
adding buffers help, or else you may want to make sure that each path is balanced and the input arrives together

The glitches are not really a problem if the results are correct in the end, however you may want to deal with them to reduce power consumption. But yeah like martianunlimited says, if the paths all have similar length then there will be less glitching.

This post has been edited by ikanayam: Nov 29 2005, 01:14 PM

It's finally done... final layout... almost 48 hours no sleep... project competition in a few hours... need... a nap...



reduced the size from 4600 um sq to 3600 um sq. Hope this will be enough for t3h win!

martianunlimited,ikanayam, Thanx 4 the help

//ikanayam, all the best to u.


I'm not sure why the result is like that. Sigh.....
Just trying to do like:
(A.B.L3 + A.B'.L2 + A.B'.L2 + A'B'.L0)' '
= ( (A.B.L3)' . (A.B'.L2)' . (A.B'.L2)' . (A'B'.L0)' )'

but kenot work





Attached thumbnail(s)

This is the original one (without converting to NAND) and its results:






Attached thumbnail(s)

Ok, i think the problem is that you are using the brackets wrong. I am not familiar with VHDL, but i think they all behave the same when it comes to the basics :P

(a NAND b) NAND l3 = ((A.B)'.L3)'

which is not the same as
a NAND b NAND l3 = (A.B.L3)'

So you probably want to do it like the 2nd one. Remove the brackets and you should be good.

This post has been edited by ikanayam: Dec 3 2005, 01:07 AM

Ikan is right, there is no operator precedence, and it's just left to right (i think you can look up your maths text book to find the precedence order, but nand, and,or and nor all have the same precedence; your de'morgans feels wrong though, you should have a NOR somewhere in your translation

Anyway, if you are willing to use NORs... try this instead (i used something called bubble technique (draw the logic with AND gates, then add bubbles. note: a' + b' = ( a . B )' and a'. b' = ( a + B )' )
S1 = (B NAND L3) NOR A_not ;
S2 = (A NAND L2) NOR B;
S3 = (B NAND L1) NOR A;
S4 = ((B_not NAND L0) NOR A; (don't really like this, but it's the best we can get); alternatively we can also use (A_not NAND L0) NOR B; your call, (you should decide base on which of the 2 signals switches more or have the higher loading, i chose the first one because the second one will give B 4 fan outs (but you save 1 logic gate (B_not is not used at all)

O = ( S1 nor S2 ) NAND (s3 nor S4)
or rather net1 = S1 NOR S2;
net2 = S3 NOR S4;
O = net1 NAND net2;

RTL design is also an artform... too bad i am dealing with mostly schematics. and don't have chance to optimize logic gates

I double checked the demorgan i am sure there was a mistake..
(A NAND B ) NAND L3 would have given you... ; (the smiley is irritating)
A AND B OR L3_not (you can check the waveform)

P/S Ikan, keep up updated ya. We will have a celebration on this thread if you win (if you don't then we will drown our sorrow with virtual booze)

This post has been edited by martianunlimited: Dec 3 2005, 08:57 AM

lol, i was so blur to notice last nite
btw, i'm using a NAND b NAND l3 at 1st, but the NAND syntax doesnt allow me to do so, and the compiler asked me to put into bracket form.


thanx for your long feedback
anyway, i think my de morgan should be ok (pls refer to the diagram attached). I've tested with a set of input and it is identical to the original AND-OR. Maybe i should try your method as quoted above
Hmm... how about building custom gate with vhdl
maybe i'll js define NAND3 component with this function:
output <= NOT (x AND y AND z);

well, fishy, we not only celebrate here if u win, but oso in the pizza


Attached thumbnail(s)

ahhh... memories.. that stuff use to give me nightmares.... 24 hours in the lab.. smelly and squiting my eyes to see if there's any cross over wires...

as your project... why not build a Triple DES encryption chip?

Actually i meant the demorgan of A AND B AND S3; it should be A NAND S3 NOR B_not and not
A NAND B NAND S3

Err I am confused... according to your diagram S0-S3 is an input not the output of the AND3, anyway, from the circuit diagram i can see some possible optimization opportunity using Quin-McClusky.
Without using the 3-fanin logics, i believe that the equations i gave one of the most simplified. (of course O = NAND(NAND(A,B,S3),NAND(A,B',S2),NAND(A',B,S1),NAND(A',B',S0)) is even better than what anybody else here can give

I agree, a NAND3 macro will make your life a lot easier; (build the NAND4 and NOR3 and NOR4 while you are at it)

Btw, this is a mux right? why don't you use the case statement instead?
(have to look it up.. but it looks something like)

select := A & B; (concatenate the 2 bits)

CASE select IS
WHEN "00" => O <= S0;
WHEN "01" => O <= S1;
WHEN "10" => O <= S2;
WHEN "11" => O <= S3;
END CASE;

(Or are you trying to synthesize the codes?)

This post has been edited by martianunlimited: Dec 3 2005, 10:31 AM

haha, sorry. actually the diagram is drawn long ago (during my 1st sem). The naming is not updated yet. the S3 -> S0 in diagram is actually the L3 -> L0 in the code

Well, this is not a MUX actually, more like a 4-bit selector. MUX implementation will take 2x more transistors and delays. This design has 16 functions actually, but i only choose 4 of them due to the limitation of 20 instructions only for my FYP.

btw, wat is "Quin-McClusky", hahaha.

Here is the comparison of this design and the mux approach.

This post has been edited by charge-n-go: Dec 3 2005, 10:55 AM

err.. the left circuit is still a mux, (X and Y is the select and S0-S3 are the inputs) Just map the following

Left -> Right
X=>S0
Y=>S1;

S3 => output of NOT;
S2 => output of XOR;
S1=> output of OR and
S0 => output of AND

The bottom mux circiut on the right is identical to the left circuit

Quine McCluskey (I can never spell that properly, hence i keep using the name QM) is a reduction technique to reduce the logic to a SOP (sum of products). QM gives most benefit when you are dealing with a lot of outputs (eg. BCD convertor, LCD interface), otherwise K-Map would be easier (i suggested QM because you have 6 inputs, and it's not easy to build a 6 input K-Map)

http://en.wikipedia.org/wiki/Quine-McCluskey_algorithm
(Using QM on my digital clock circuit got me a A+ for "digital logic and design") (i didn't know that there was a 2 digit decimal->BCD then a BCD->LCD convertor and i actually did a 6 bit binary number -> LCD (14 outputs.. VERY painful to reduce... (especially for the LCD for the first digit)

This post has been edited by martianunlimited: Dec 3 2005, 11:37 AM