Haha. gimme a while need to look up what in the world is a veterbi decoder....
Okie, it's a transciever with encoder/decoder.  Sorry I am not involved with with these types of circuits. And i can't believe that i need to read up on trellis coding to remember how it works. Sigh that's what happens when you don't touch communication for a few years...

anyway I assume you already know the information here... http://www2.ing.puc.cl/~iee3552/TCM.PDF

Based on the block diagram here, This is what i will do, i will implement the decoder,  (and control blocks) in verilog/VHDL or systemC (your choice, just so that i can synthesize it and save myself time). You will have to blackbox the demodulator block; (allocate some space for your layout so that the place and route tool won't accidentally route around that area and cause problems with your routing later).
The circuit demodulator block will need to be designed by hand; from the diagram it appears that all the viterbi decoder need is the recieved data. so just send the recieved data; with a clock;  and the control block should be sending and recieving control signals to both the demodulator and the decoder.

After you have your demodulator circuit, then just draw the layout and connect it to the verilog synthesized portion.

(verilog for viterbi decoder: http://www-ee.eng.hawaii.edu/~msmith/ASICs...11/CH11.12.htm) I shouldn't be doing this but i wanted to verify whether or not the decoder is really synthesizable

Side note: regarding your question to convert verilog to schematic, most synthesis tools, and formal verification tools should have that capability (some accepts only synthesized verilog so you may need to do just that)

Just curious is this wired or wireless? It's possible to build an antenna on a chip, but i have no idea how it's done.

haha, probably should have stated my question properly, how do you model a Viterbi decoder in terms functional block but anyways, don't think u might remember back since u haven't been touching this for some time
coz i realize to implement the algorithm/trellis diagram in terms of hardware is kinda headache......
i already know the process that you mentioned to me(coz my supervisor did brief me on a brief process flow), thanks anyways
anyways, mind telling me wat synthesis tools is that? coz our college don't seem to have that tool(unless our supervisor doesn't want us to use)
actually currently i'm avoiding the black box process and try to model it using functional block immediately, that way i can model the schematic form much more easily

Synthesis tools basically converts verilog statements and equations to logic gates/flops (so the answer is yes..)

guys, i hav a question here, regarding FPU. i'm currently working on normalizing the result, i hav somehow figured out the algo to do it, but i would like to know if there's any good algo for it. thanks

okie, thanks for the feedback. my goal is to achieve minimum delay in terms of gate level and the fastest algo. And i need to normalize an 8-bit result.

any more info needed?

my fp format is :- 16-bit only, 1 for sign bit, 7 for biased exponent, 8 for mantissa, support denormals aso

now after add/sub the mantissa, i need to normalize it to 0.1XXXXXXX before storing the result.

1XXX will be stored, so there will b no implied bit after the decimal place
is there any way to do it within one clock cycle, at gate level instead of transistor level?

halo, maybe can ask shabiul for help (JKJK). According to martianunlimited suggestions previously, i already have a few 8-bit adders for you. Choose one to suit yr multi adder FP unit design, hehehe.
btw, anybody knows how to calculate the delay due to the increase of fan-in? Thanx

Yes you can do it in one clock, you need to use a barrel shifter or eight 8-to-1 multiplexors. Both of which will consume a significant amount of hardware. You'll also need a subtractor to determine the difference in the exponents to give you the number of bits you have to shift.

hm...so for example, the result is something like 0.00001010, do u mean to count the number of zeros and then shift accordingly to make it 0.10100000?