After Intel's price cuts we mentioned that despite Penryn's imminent launch, CPUs had gotten too affordable to pass up building a system now if you needed. Now that we have a general idea of clock-for-clock performance differences between Conroe and Wolfdale, we're not nearly as worried about recommending that you build systems today as we once were. There's no doubt that Wolfdale is faster clock-for-clock, but keep in mind that you won't see Wolfdale until Q1 of next year and the performance advantage simply isn't great enough to justify delaying a purchase by 6+ months if you need a system now.

AMD seems quite confident that Phenom will be able to compete with Conroe/Kentsfield; if the race is really close between those cores, Penryn could be exactly what Intel needs to remain technically ahead in performance. If Phenom is significantly faster than Conroe/Kentsfield, then it doesn't look like Penryn will be able to save Intel. We should know for sure which scenario will pan out in the not too distant future.

Source : http://www.dailytech.com/article.aspx?newsid=8585

2008 Octal-Core, just my aim, dun like the words "4" cores, LOL, wondering when Intel will match the pair of quad-core become direct combination of Octal-cores like old quad-core kentsfield method ?

This post has been edited by cinbao: Aug 25 2007, 08:22 PM

Octal-core on MCM is as useless as Quad SLI. (For Intel anyway, DAAMIT seems to be rather keen on their Shanghai )
Intel would likely need a 2+Gigahertz FSB for that, and they have problems pushing even 1666 nowadays.

Word has it that the next major marchitecture revamp (Nehalem) *might* not have the integrated memory controller (what's been helping AMD so much) on desktop chips, but unless they overcome their FSB woes, MCM-ing quads or four duos will be a tough take from a performance standpoint.

Nehalem will not have IMC on mainstream desktop and laptops.
IMC on extreme edition chip -> maybe.

Maybe P45 and X48 will have liquid cooling then.
(And getting only the XE with IMC doesn't solve platform unity, so P45 still needs crazy cooling )

Is it possible the mainstream still be on LGA 775? Although it may require totally new chipset.

i hope so. dont follow suit AMD's step to dump those poor 939 users. lol...

... still haven't forgiven amd for it.

Ya, since the case of sc939, I was afraid to go back with AMD ...

FSB ? I was wonder is that Intel will not adopt the Hyper Transport Consortium technology ? the HTT do not belong to AMD, so if Intel got the FSB bottleneck problem to push up 2000 Ghz, but HTT was the way brightness future , why invest so much to re-engineer the Proc Core architecture ? (Imagine Core 3 series to overcome bottleneck issues due to the limitation of FSB) ... Hmmm all about money matter ?


I wish that my current LGA 775 still can support the Nehalem series onward, but reality is always cruel ...

This post has been edited by cinbao: Aug 26 2007, 02:10 AM

HyperTransport was derived from DEC/Alpha EV7 bus (free license from Intel actually!).... Why doesn't Intel use it? Beats me!

Seems to me that HTT isn't something easy to implement without a new marchitechture design (Core 2 is a heavily redone Core/Pentium-M, but it still has almost the same roots, quad pumped FSB etc...) and Intel was kinda scrambling to get Conroe to market, HTT didn't seem a priority compared to sweeping marchitectural changes...

Well, poo poo on 'em

(Also noted that it seems DAAMIT had most of the NexGen and DEC engineers that saved their butt with the Athlon)

This post has been edited by X.E.D: Aug 26 2007, 07:24 AM

MCMing 2 quad core dies will still have 2 external FSB interfaces, much like the current quad core chips. I still don't see the need for a IMC/HTT equivalent in a single die/lower end versions of Nehalem (unless it uses a low pin count serial interface). DDR/HTT pads use a lot of space on the chip, and don't scale well with new processes. Just look at how much space they take on Barcelona. The dual core version will have an even higher percentage of chip area dedicated simply to driving external pins.


Intel has not changed the socket for a long time, but every new chip seems to need a new chipset. What's the difference? It's even worse this way.


You need coherent HTT links for CPUs, and coherent HTT belongs to AMD alone, and needs to be licenced from them. Obviously intel doesn't want to pay royalty to AMD for every single chip that they make using this.


Messing with the internal microarchitecture is a lot more difficult than an external bus interface. The external interface and the internal microarchitecture can be completely orthogonal, as Nehalem will show. This is how it is generally done, the bus unit is developed independently and parallel to microarchitecture. I would not be surprised if intel already has versions of its Core2 with versions of an IMC or CSI for internal testing.

i don see any need of Penryn if Vista is not "usable"...

The whole platform for Intel will be quite fragmented in the next couple of years.
You'll have versions with IMC, without IMC etc even when all segments (server/desktop/laptop) will be using the same core.

LOL, well, coherent HTT?

Last time, Honda V-Tech technology was licensed by itself, nowadays, Toyota make itself VVT-i /VVTL-i (this 1 really can even with i-Vtec), do Toyota pay Honda any royalty?

Nissan has NEO VVL / C-VTC

Perodua has DVVT

Gen2 has Campro / CPS

Hyundai has HIVEC

Mitsubishi has MIVEC

Do they all pay Honda royalty by having those variable timing technology ?



back to topic, I think Intel can straight away go to HTT version 3.0, is that coherent of HTT 3.0 belongs to AMD too?

If not, would u think FSB still can last how long?

All coherent HTT belongs to AMD. Obviously they won't give that one away for free. Intel is already working on its own interconnect, which probably will have more similarities to pci-e than HTT. Very strong NIH syndrome at intel.

I would imagine AMD owns a good number of patents/IP on cHTT and given how everyone in the US likes to sue each other licensing would be the safest way to go.
Or it could just be NIH mentality.

Since u brought it up. Most ppl think Honda invented variable valve timing, which is a crock. Honda DID NOT invent Variable Valve timing. The very beginnings of variable valve timing started with Alfa Romeo a long long long long time ago. They all work in different ways though they're all valve timing n lift stuff. If any1 were to copy the VTEC exactly, Honda will have every right to sue. Just as in, if Intel uses the same exact thing as AMD then they will hafta pay.

Nahalem may have hyper threading back.

Nehalem WILL have hyperthreading/SMT back.

Will but it is rather arguable whether ANY consumer centric app would even utilize enough threads to even make use of HT...

Server apps harly have any use for HT IIRC. IMO they shouldn't be splitting more resources into more threads, rather trying the reverse instead- if that is possible without much intervention from native OS.

HT only brings more hot spot on cpu and generally increase heat and power consumption. That's why for now they didnt implement it.

Let's just say that HT was not exactly very good SMT, on a not very good processor core. Nehalem's SMT implementation will probably be substantially different.

Why would you want to put even more cores into a single thread when many resources on each core are sitting idle as it is now? It's bad for perf/watt. SMT done well generally improves perf/watt.


A form of SMT is probably already in Core2 chips, but not enabled for public use. It's not trivial to implement, because they can't just take "HT" from the P4 and put it in there. Completely different chips, so completely different approaches. HT in p4 actually does help many well written applications. At the time most applications were not designed for multithreaded systems, but now they are. So i think it's a good time to reintroduce SMT now. Of course increasing utilization will increase power and hot spots, but it's still better than idle units that are leaking power doing nothing.

Ever heard of Sun's Niagara (UltraSparc T1) chips? 8 cores with 4 threads per core = 32 thread monster.
Now there's Niagara2 (UltraSparc T2) -> 8 cores with 8 threads per core = 64 thread beast.
These are ultra powerful web/transaction servers.

Reverse-HT seems to be a big myth propogated by the AMD fanbois based on some dubios comments from the Inq.


That's where the hi-k dielectric in 45nm comes in to play.

Hi-k dielectric helps with gate leakage, but it does not do much for sub-threshold leakage, which is as much of a problem. Increased utilization is usually preferable in a wide chip such as the core2.

Anyway, as long as who capture the performance crown no matter of slightly higher power consumption will be chosen.

yup u rite,...
power consumption must be considered in order to archive maximum performance...

I liked the Niagara 2 design a lot, but all in all the design itself would have no place in a x86 consumer centric market (even if it ran x86!)
You would have say, 16 threads max. utilized at one moment. Coders don't prefer coding massive parallel code unless it comes with noticible benefits (which aren't required on the consumer market yet)

Generally you want less cores as possible for less complexity while maintaining the highest speed. There are quite a lot of apps that only scale good to dual-core ATM- quads don't even provide a substantial increase. So why more focus on getting the most juice out of your already very capable 4-core? You know for once I'd leak some power.

HT had a nice increase because the P4 was essentially single cored, and most apps tested on it were taking advantage of optimizations for workstations with dual+ Xeons/Opterons I presume.