Octal-core on MCM is as useless as Quad SLI. (For Intel anyway, DAAMIT seems to be rather keen on their Shanghai )
Intel would likely need a 2+Gigahertz FSB for that, and they have problems pushing even 1666 nowadays.

Word has it that the next major marchitecture revamp (Nehalem) *might* not have the integrated memory controller (what's been helping AMD so much) on desktop chips, but unless they overcome their FSB woes, MCM-ing quads or four duos will be a tough take from a performance standpoint.

Maybe P45 and X48 will have liquid cooling then.
(And getting only the XE with IMC doesn't solve platform unity, so P45 still needs crazy cooling )

Seems to me that HTT isn't something easy to implement without a new marchitechture design (Core 2 is a heavily redone Core/Pentium-M, but it still has almost the same roots, quad pumped FSB etc...) and Intel was kinda scrambling to get Conroe to market, HTT didn't seem a priority compared to sweeping marchitectural changes...

Well, poo poo on 'em

(Also noted that it seems DAAMIT had most of the NexGen and DEC engineers that saved their butt with the Athlon)

This post has been edited by X.E.D: Aug 26 2007, 07:24 AM

Will but it is rather arguable whether ANY consumer centric app would even utilize enough threads to even make use of HT...

Server apps harly have any use for HT IIRC. IMO they shouldn't be splitting more resources into more threads, rather trying the reverse instead- if that is possible without much intervention from native OS.

I liked the Niagara 2 design a lot, but all in all the design itself would have no place in a x86 consumer centric market (even if it ran x86!)
You would have say, 16 threads max. utilized at one moment. Coders don't prefer coding massive parallel code unless it comes with noticible benefits (which aren't required on the consumer market yet)

Generally you want less cores as possible for less complexity while maintaining the highest speed. There are quite a lot of apps that only scale good to dual-core ATM- quads don't even provide a substantial increase. So why more focus on getting the most juice out of your already very capable 4-core? You know for once I'd leak some power.

HT had a nice increase because the P4 was essentially single cored, and most apps tested on it were taking advantage of optimizations for workstations with dual+ Xeons/Opterons I presume.