QUOTE(X.E.D @ Aug 25 2007, 09:35 AM)
Octal-core on MCM is as useless as Quad SLI.

(For Intel anyway, DAAMIT seems to be rather keen on their Shanghai

)
Intel would likely need a 2+Gigahertz FSB for that, and they have problems pushing even 1666 nowadays.
Word has it that the next major marchitecture revamp (Nehalem) *might* not have the integrated memory controller (what's been helping AMD so much) on desktop chips, but unless they overcome their FSB woes, MCM-ing quads or four duos will be a tough take from a performance standpoint.
MCMing 2 quad core dies will still have 2 external FSB interfaces, much like the current quad core chips. I still don't see the need for a IMC/HTT equivalent in a single die/lower end versions of Nehalem (unless it uses a low pin count serial interface). DDR/HTT pads use a lot of space on the chip, and don't scale well with new processes. Just look at how much space they take on Barcelona. The dual core version will have an even higher percentage of chip area dedicated simply to driving external pins.
QUOTE(SpikeTwo @ Aug 25 2007, 11:53 AM)
i hope so. dont follow suit AMD's step to dump those poor 939 users. lol...

Intel has not changed the socket for a long time, but every new chip seems to need a new chipset. What's the difference? It's even worse this way.
QUOTE(cinbao @ Aug 25 2007, 12:50 PM)
Ya, since the case of sc939, I was afraid to go back with AMD ...
FSB ? I was wonder is that Intel will not adopt the Hyper Transport Consortium technology ? the HTT do not belong to AMD, so if Intel got the FSB bottleneck problem to push up 2000 Ghz, but HTT was the way brightness future , why invest so much to re-engineer the Proc Core architecture ? (Imagine Core 3 series to overcome bottleneck issues due to the limitation of FSB) ... Hmmm all about money matter ?
I wish that my current LGA 775 still can support the Nehalem series onward, but reality is always cruel ...

You need coherent HTT links for CPUs, and coherent HTT belongs to AMD alone, and needs to be licenced from them. Obviously intel doesn't want to pay royalty to AMD for every single chip that they make using this.
QUOTE(X.E.D @ Aug 25 2007, 06:23 PM)
Seems to me that HTT isn't something easy to implement without a new marchitechture design (Core 2 is a heavily redone Core/Pentium-M, but it still has almost the same roots, quad pumped FSB etc...) and Intel was kinda scrambling to get Conroe to market, HTT didn't seem a priority compared to sweeping marchitectural changes...
Well, poo poo on 'em

(Also noted that it seems DAAMIT had most of the NexGen and DEC engineers that saved their butt with the Athlon)
Messing with the internal microarchitecture is a lot more difficult than an external bus interface. The external interface and the internal microarchitecture can be completely orthogonal, as Nehalem will show. This is how it is generally done, the bus unit is developed independently and parallel to microarchitecture. I would not be surprised if intel already has versions of its Core2 with versions of an IMC or CSI for internal testing.