Nice catch. Seems to me like the core microarchitecture itself changes less than Core->Core2 (but then we could have already guessed that from what we knew before). I was most interested in the cache/prefetching changes, but seems like it also has not changed much. Cache prefetching is still much less fancy that the Core2. The L2/L3 caches are still just large victim caches like the current K8, no prefetching done there. Very interesting and fundamental difference from intel's cache design/hierarchy. I look forward to seeing how Nehalem deals with caching. Seems like AMD focused a lot of improvements on the memory controller and system architecture (the xbar on the 10h looks pretty big). Stride prefetcher and prefetch buffers for the mem controller. HT3.