if barcelona really good....AMD sure will show all other benchmark for us...

but its seem barcelona just can beat in certain suite only ....

not like when C2D beat AMD

It does go through the crossbar in trasferring data between cores, unless the course given here is misleading

Xbitlabs did some testing and they proved it went through the FSB by looking at the latency numbers IIRC.

Chargey and I had a chat about that, and it's either there was a problem with the testing methods (unlikely), or it really is that way. Seems that it needs either a unified cache at some level or a smarter coherence protocol controller on the xbar in order to make that happen.

The original paper detailing the MOESI protocol (for the Pirahna chip, which is like the father of the A64) used the unified L2 controller to handle intra-core coherence.

Hey dude, still FSB? I think you Intel too much lately

Anyway, even the data is taken from RAM, it still goes through the crossbar in this fashion: RAM -> DRAM controller -> mem controller -> crossbar -> SRI -> cache. MOESI / MESI is so stupid that it wont transfer data from core 0 to core 1 in a more direct way. (when going from 'E' state to 'S' state).

This post has been edited by charge-n-go: Apr 25 2007, 03:19 PM

^ it's more like the coherency controller wasn't smart enough to take advantage of MOESI than a weakness in the protocol itself. It can be done with MOESI given the right implementation (i.e. how it's done in Pirahna).

Hopefully barcelona takes care of this. It does have a shared L3 after all, which should make things a lot easier if they do it right.

This post has been edited by ikanayam: Apr 25 2007, 03:32 PM

yeah you got the point. The states can actually remain the same, but the implementation could be different.

Hmm.. mind to post up the piranha details in engineering thread?

I don't think i can make the paper public, however you know where to find me....

I have to look for it first. I have it in print, but i have to find the digital copy.

intel has both penryn and nehalem

now amd's hoping so much on barcelona which i think is all bit of a rush kan?
the 65nm processors from amd sucks big time
i dunno where they get the idea to spend all those money in worthless rnd
anyways, i've always been a fanboy to amd
if and when barcelona comes out (Q4 2007 right?), i'd say intel would still be the king the next day with their better processors

barcelona cannot beat penryn..
like X2900 XTX cannot beat 8800 GTX.......
dailytech

can u provide the link...

This post has been edited by arjuna_mfna: May 3 2007, 12:47 PM

http://dailytech.com/ATI+Radeon+HD+2900+XT...article7052.htm

I think he is mentioning about this.

This post has been edited by raymond5105: May 3 2007, 08:19 PM

that old thing.. it oem and run on gddr3, btw retail one will come with gddr4

then X2900 XTX cant beat 8800 ultra

why this Penryn thread morph into a graphic vs graphic card thread

anyway, it seems that SSE4 can boost performance by up to 50%. i dunno how true is that. but it seems that previous SSE versions doesnt boost performance that much. anyone hav more info on these?

This post has been edited by edwin3210: May 7 2007, 10:25 AM

The key word is "for certain apps". And yes, previous SSE versions could also boost performance "for certain apps" by that much or even more.

for SSE, it's more on software optimization. software need to be coded to support it right?

Any SSE needs software support.

i thought sse is somekind of shortcut the cpu use to execute the process...like combining the same order..

SSE are instruction sets, that means you need to use the assembly instruction in order to use the feature supported by SSE.