Then what are u referring to?
It is either Kentsfield, Penryn or Barcelona only.

So u mean, Barcelona doesn't share the cache, and Penryn does? How about Kentsfield, isn't it the same, y Penryn only?

There is no 'real quad' and 'fake quad'. Barcelona, Penryn and Kentsfield are all Quad Cores. If seriously wanna define 'Fake Quad', Pentium D EE with 2 physical cores and 2 logical cores is a good example.

You are the one who starts : "In fact there is: True Quad doesnt share the cache". So i was really interested how True Quad can be defined this way.
In fact, your statement said : Penryn / Kentsfield is a 'true' quad because they don't share cache between sites. Barcelona shared their cache among all cores, so it is not a 'true' quad. This is a misleading info dude.

there is no 'true' and 'fake' quad. If a CPU has 4 physical cores in the same package, it is a quad core.

Intel uses non-monolithic approach to simplify the design with some sacrifice in performance, while AMD uses monolithic approach to have higher performance but takes longer time to design.

No, the design time will not be the same. In terms of architecture, you need a redesign the intercore communications and cache if it is a monolithic approach, not to mention about circuit and layout optimization. For Kentsfield, all you need is to pack 2x C2D into a package, where the architecture and circuit are almost identical. Probably the power management logic and coherency/EBL need some changes, that's all. MCM makes sense to save cost and design effort, but sacrificing the performance & efficiency. This is why Intel can debut the 1st quad core much faster than AMD.

This post has been edited by charge-n-go: Apr 24 2007, 01:02 PM

As I said, kentsfield and barcelona are real quad cores, as they has 4 physical cores. The 4 processing cores ARE there. In engineering term, it is called the Monolithic vs Non-monolithic approach. The real or fake stuff are just some marketing terms to confuse the public.


What are u trying to say? Kentsfield has its own cache in individual core also. The definition of native quad core doesnt care about the cache at all. The cache system in Barcelona is simply implementation specific but has nothing to do with Native Quad Core design. The word "true" is misleading, but "native" describes the monolithic approach best.


you are wrong again. intel doesnt stick 2x dual core into one processor die. they are simply packaged together as single CPU unit. the word 'die' means 1 silicon --> the monolithic approach. As long as the applications have multi-threading support, it will have performance increment for sure. No special optimization is needed.

haha, don't say tat. i m also referring to some internal documentations to answer BlackThyra87

haha, although i worked in intel, but there are some amd overview classes over here.
You are right, the core to core transfer is done via crossbar. It is just like the D-link or whatever intranet switch we use at home. NB is the centralize controller to determine what data to be transferred via crossbar, and serves all requests from the cores. Well, i think the fact that NB is built-in into K8 doesn't cause as much penalty as C2D / P4 where the NB is external.

from the attached image, K8's NB is called the System Request Interface.


^ oh shooot, this is a single core K8. a dual core K8 has the same structure btw, js adding another core side by side with the 1st core.

Image taken from Mindshare Slides (www.mindshare.com)

This post has been edited by charge-n-go: Apr 24 2007, 06:42 PM

It does go through the crossbar in trasferring data between cores, unless the course given here is misleading

Hey dude, still FSB? I think you Intel too much lately

Anyway, even the data is taken from RAM, it still goes through the crossbar in this fashion: RAM -> DRAM controller -> mem controller -> crossbar -> SRI -> cache. MOESI / MESI is so stupid that it wont transfer data from core 0 to core 1 in a more direct way. (when going from 'E' state to 'S' state).

This post has been edited by charge-n-go: Apr 25 2007, 03:19 PM

yeah you got the point. The states can actually remain the same, but the implementation could be different.

Hmm.. mind to post up the piranha details in engineering thread?

SSE are instruction sets, that means you need to use the assembly instruction in order to use the feature supported by SSE.