Willamette Block diagram

Prescott Block diagram

No Northwood loving, unfortunately. Both diagrams were cut-n-paste from pdf articles available at the link above (prescott on the front page, willie in the archives). Anyway that ought to put to rest the 128 bit wide bus width from L2. So the mystery remains where does the bottleneck lie?
nUtZ`: L2 cache line length is 128 bytes long on all the P4 implementations, apparently, and the L1 D-cache line is also 64 bytes long throughout. You raised a good question about data alignment.
Not sure if the increasing the L1 set associativity from 4-way to 8-ways has anything to do with the lacklustre performance. I mean, after x mod 4 vs x mod 8 is just a 1-bit difference;
This post has been edited by silkworm: Apr 22 2004, 03:54 PM
Apr 22 2004, 12:40 PM
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