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> RAM Handbook, updating ... zlol 23/12/07

charge-n-go
post Jan 15 2006, 01:34 PM

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Some additional info for this thread wink.gif

Compromises between timing and clock speed

First of all, FSB or HTT has nothing to do with timing. The timing is for RAM only.


What's the benefit of low timing?
- memory controller can access the RAM chip faster
- It can access small and random data at faster rate.
- Hence, u can feel the responsiveness and smoothness when timing is lowered.

What's the benefit of high bandwidth (high clock speed).
- high bandwidth enabled more data to transfer to and from CPU in 1 second.
- benefit when dealing with big size data.


What software is better for low timing / high bandwidth
- eg. DDR600 at 3-4-4-8.
- The initial response might be a bit slow, due to high timing.
- However, once the RAM is accessed, the high bandwidth allows massive data transfer.
- Programs like Winzip doesnt randomly access the RAM too much.
- So once the RAM is accessed, the memory bandwidth is more important to complete the task quickly.
- Programs like MS words deal with very small piece of data.
- Hence lower timing has better benefit, bcoz it can access the data quickly.


What's the relation between timing and bandwidth

* note: this is js a rough estimation.

- eg. DDR400 2-3-3-7. <-- has CAS latency of 2.
"2" means the delay measured in clock cycles. So, at 200MHz, 2 Hz is wasted to 'wait' for CAS.

- The actual time delay per clock = 1/200MHz = 5 nanosecond (ns). When 2 Hz is wasted, that means the memory controller have to wait 2(5 ns) = 10ns to access the Column (CAS).

- Hence, the time delay is closely related to clock speed.

- Bandwidth also related to clock speed, with the formula (N-bit / 8) x clock speed

- Therefore, time delay is related to bandwidth.

- DDR400 (200MHz) with CL2.0 has the same CAS delay as DDR600 (300MHz) with CL3.0.

calculation:
1/200MHz x 2 = 10ns.
1/300MHz x 3 = 10ns.
jinaun
post Jan 15 2006, 04:29 PM

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QUOTE(mynewuser @ Jan 15 2006, 03:13 PM)
Very informative topic. Btw, HYMD264646D8J-D43 is what chip?
*
its hynix D43 series

HY stands for Hynix and D43 means for DDR400 at C3
Irishcoffee
post Jan 15 2006, 08:20 PM

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Thx 4 your great information abt RAM
now i know my D43 Ram suxx
"This might not be the ideal ram choice for an Athlon XP setup"
Mowgli
post Jan 16 2006, 02:25 AM

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nice compilation dude.....very intresting read n i am sure wud help lotsa ppl round here...
briangan
post Jan 16 2006, 02:46 AM

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really really nice topic u got here...
all hands up for u...
good job...
PowerSlide
post Jan 16 2006, 03:27 AM

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recently ive seen alot of KVR with mosel vitalic chippy

even bought a stick n it goes as high 235mhz in stock timing of 3-3-3-8

thumbup.gif
jinaun
post Jan 16 2006, 01:24 PM

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QUOTE(charge-n-go @ Jan 15 2006, 01:34 PM)
Some additional info for this thread wink.gif

Compromises between timing and clock speed

First of all, FSB or HTT has nothing to do with timing. The timing is for RAM only.
What's the benefit of low timing?
- memory controller can access the RAM chip faster
- It can access small and random data at faster rate.
- Hence, u can feel the responsiveness and smoothness when timing is lowered.

What's the benefit of high bandwidth (high clock speed).
- high bandwidth enabled more data to transfer to and from CPU in 1 second.
- benefit when dealing with big size data.
What software is better for low timing / high bandwidth
- eg. DDR600 at 3-4-4-8.
- The initial response might be a bit slow, due to high timing.
- However, once the RAM is accessed, the high bandwidth allows massive data transfer.
- Programs like Winzip doesnt randomly access the RAM too much.
- So once the RAM is accessed, the memory bandwidth is more important to complete the task quickly.
- Programs like MS words deal with very small piece of data.
- Hence lower timing has better benefit, bcoz it can access the data quickly.
What's the relation between timing and bandwidth

* note: this is js a rough estimation.

- eg. DDR400 2-3-3-7. <-- has CAS latency of 2.
"2" means the delay measured in clock cycles. So, at 200MHz, 2 Hz is wasted to 'wait' for CAS.

- The actual time delay per clock = 1/200MHz = 5 nanosecond (ns). When 2 Hz is wasted, that means the memory controller have to wait 2(5 ns) = 10ns to access the Column (CAS).

- Hence, the time delay is closely related to clock speed.

- Bandwidth also related to clock speed, with the formula (N-bit / 8) x clock speed

- Therefore, time delay is related to bandwidth.

- DDR400 (200MHz) with CL2.0 has the same CAS delay as DDR600 (300MHz) with CL3.0.

calculation:
1/200MHz x 2 = 10ns.
1/300MHz x 3 = 10ns.
*
Good Information!

btw.. how do i move such types of posts into first page of this thread...

silkworm
post Jan 16 2006, 03:20 PM

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Way to go chargey, btw, some minor corrections for ya:
QUOTE(charge-n-go @ Jan 15 2006, 01:34 PM)
- eg. DDR400 2-3-3-7. <-- has CAS latency of 2.
"2" means the delay measured in clock cycles. So, at 200MHz, 2 Hz is wasted to 'wait' for CAS.

- The actual time delay per clock = 1/200MHz = 5 nanosecond (ns). When 2 Hz is wasted, that means the memory controller have to wait 2(5 ns) = 10ns to access the Column (CAS).
You mean 2 clock ticks. 2Hz has an interval of 500ms which is way too long. tongue.gif
briangan
post Jan 17 2006, 01:58 AM

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jinaun... i got some pics of the of the Infineon BT-6 Chipset...
do get it here...

http://forum.lowyat.net/index.php?act=ST&f...=0#entry5724203

user posted image

anyway...
i got it to run at 241MHz/DDR482 on 2.5-3-3-5 1T setting...
memtest stable...


charge-n-go
post Jan 18 2006, 09:08 PM

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QUOTE(jinaun @ Jan 16 2006, 01:24 PM)
Good Information!

btw.. how do i move such types of posts into first page of this thread...
*
you can put the info posted by others in another reserved post, or u can take my info and rephrase it in yr own way wink.gif


QUOTE(silkworm @ Jan 16 2006, 03:20 PM)
Way to go chargey, btw, some minor corrections for ya:
You mean 2 clock ticks. 2Hz has an interval of 500ms which is way too long. tongue.gif
*
Aikkss, wat a stupid mistake laugh.gif
thanx for the correction.
Redundant
post Jan 21 2006, 02:09 PM

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i have a kingston KVR DDR333 512MB on my intel i845pesv motherboard, can i add another corsair / kingston DDR400 512MB to my 2nd slot? since it's hard to find DDR333 now ><
thanks in advance!

This post has been edited by Redundant: Jan 21 2006, 02:09 PM
kanethesun
post Jan 21 2006, 06:58 PM

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hmmm, just check my ram
its V58c2256804SCI5B
is is the series of Mosel Vitelic 5ns?
jinaun
post Jan 21 2006, 07:05 PM

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QUOTE(kanethesun @ Jan 21 2006, 06:58 PM)
hmmm, just check my ram
its V58c2256804SCI5B
is is the series of Mosel Vitelic 5ns?
*
probably yes.. but have to check the whitepaper to be sure...will follow up later...

*it seems to be CI revision compared to AT rev found in the ram handbook guide
kanethesun
post Jan 21 2006, 07:17 PM

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yalo, hmmm, can do up to 245 1:1
but tried for days, reduce from 245 to 230
still cannot prime stable, 245 memtest stable
timing 2.5-3-3-6 for 245 memtest stable vdimm 2.6
dont know whether it likes voltage or not
europology
post Jan 28 2006, 04:26 PM

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QUOTE(Redundant @ Jan 21 2006, 02:09 PM)
i have a kingston KVR DDR333 512MB on my intel i845pesv motherboard, can i add another corsair / kingston DDR400 512MB to my 2nd slot? since it's hard to find DDR333 now ><
thanks in advance!
*
eh...mine oso same motherboard with u..and i oso thinking of upgrading my ram (my ram sucks...256MB at 266MHz!!!)

and btw, if u read the manual of ur motherboard, it can only support up to 333MHz of ram ler...so i think 400MHz cannot fit into it...
jinaun
post Feb 3 2006, 05:42 PM

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What are UTT Memory ?

In recent months, there seems to be an increased buzz on UTT based memory modules. What exactly is UTT memory ? UTT stands for UnTested DRAM chip. This term is used on chips which are packaged in the final backend assembly but not speed graded and sorted according to the frequency and latency categories .

There are much misconception that UTT memory modules are new and high frequency DRAM chips that just hit the market. UTT are essentially untested DRAM chip.

DRAM manufacturers are regularly releasing these UTT DRAM chips in large volume into the market distribution. There are a number of reasons why DRAM manufacturers are choosing to release the untested chips into the DRAM Spot market

One of the benefit of shipping untested Dram chips translate to "cost savings" as DRAM manufacturers can cut up to 20 percent in cost per DRAM chip by skipping chip detailed reliability burn-in and functionality testing on higher end chip testers . This effectively save time, production test capacity and shortened production cycle.

Many DRAM makers outsourced the DRAM chips testing to 3rd party testing contractors and there is a cost involved for each chip whether it is tested good or bad. In DRAM wafer fab, each DRAM wafer can be advanced probed for defects and non-conforming test to determine the yield before final packaging . The wafer with poorer yield are marked and package into chips destined to be sold as UTT chips.

Imagine the huge losses a manufacturer can incurred, if the under-performing wafers are scrapped. UTT chips are the "creative" effort of DRAM manufacturers to turn scrap losses to profit. Effectively enabling DRAM manufacturers to eliminate large quantities of untested and non-conforming chips into the market very quickly for non-PC applications such as DVD players, MP3 players, toys and low-end graphic display cards.........etc. This can be quite an sound business model if the supply of UTT chips are consistent.

user posted image

This spot price was taken from www.dramexchange.com , notice the DDR256Mb 32Mx8 ETT UTT price are listed as a commodity item. ETT is a new term known as - Effective Tested Chip which means used the same as UTT.

Most of the UTT chips are shipped blank without any noticeable marking on the chips, memory brokers buys this chips at very low price for trade. UTT chips are traded worldwide do end up in memory module manufacturing facilities worldwide for eventual assembly into Memory module application.

UTT devices are commonly seen in inexpensive or low end memory module . The frequencies and latencies varies from different batches thus requiring pre-sorting by memory testers before production assembly. In Asia, there are over several hundred small scale companies emerging selling UTT and Downgrade DRAM products.

user posted image

A Typical Unmarked 66pin DDR TSOP ( UTT ) or Downgrade chip

Majority of the UTT chips are used with low end PCB board . These UTT chips finds its way to lower end DIMM modules which are often tested only on motherboards . The tested modules are then imprinted with the respective company logo or laser imprint . Most 3rd Party manufacturers print some label that has no tracebility back to the origins of the DRAM chips.

For the lower performance DIMM module , these are typically sold with standard labeling to consumer at rock bottom price.

user posted image

UTT Chips assemble on DDR DIMM PCB board ( Chips are Winbond BH-5)

For the better performing UTT chips, most common practices are enclosing the modules with an attractive HeatSpreader, to make the DIMM modules look more appealing to the consumer

user posted image

Typical Copper Plated Heat-Spreader

It is not uncommon to see higher performance modules build with UTT Dram selling for premium price and for very high performance application. For instances , some websites are offering very high price DDR 500 Mhz 184pin Unbuffered DIMM memory running with 2-2-2 peak performance level, requiring at least 2.6 - 3.5 Volts to support this special high performance module on selected Motherboards offered by MSI,Gigabytes, ASUS......etc.

user posted image

High Performing Unbuffered DDR 500Mhz DIMM using UTT Chips with Heat-Spreader

The Winbond BH-5 chips are legendary ,the frequency of the chip can be scale beyond its rated frequency as the voltage level is raised. There are reported cases of the Bh-5 and Bh-6 chips capable of clocking at 600Mhz data-rate with very low latencies. A typical example of a high performing 3rd party DIMM module capable of overclocking beyond 500Mhz , the latency are offered in the following :

All rated timings listed is CAS-tRCD-tRP

2-2-2 means : Cas = 2 , Trp = 2 , Trcd = 2

To find rated MHz from ns, ( 1/ns x 1000 ).

PC2700 = DDR333
PC3200 = DDR400
PC3500 = DDR433
PC3700 = DDR466
PC4000 = DDR500
PC4200 = DDR533
PC4400 = DDR550
PC4800 = DDR600

DRAM industry players are not overly concerned about UTT memory module damping prices, since the flow of UTT chips into the main stream grey-market distribution channel can be regulated depending on the supply and demand of dram chips.

In the real world application, memory modules built with UTT chips may not perform with great reliability, thefore consumer often seeks for more reliable memory module build by first qulaity chips neccessary for mission critical application such as Server or highend Workstations.

With DDR2 Memory emerging as the next main stream memory wave , will there be any UTT DDR2 chip available ? The answer is 'Yes', there will always be UTT chips and downgrades dram chips irregardless of any new memory technology

The next time you find a computer advertisement in your local paper offering a 1GB Unbuffered DDR DIMM at $49 bucks or a 600Mhz DDR DIMM with a Flashy Heat-Sink , chances are this module are made with UTT chips . One gets what one pay for , so do not expect longetivity of memory module in this category.

Source : http://www.simmtester.com/page/news/showpubnews.asp?num=124

This post has been edited by jinaun: Feb 3 2006, 05:42 PM
jinaun
post Feb 3 2006, 05:48 PM

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What is a Fully Buffered DIMM Memory?

Typical DRAM memory subsystems use a stub-bus topology that requires the data signals from the memory controller be electrically connected to the data lines of every DRAM module on the bus. With as many as 72 connections in today's server designs, the signals may degrade where the bus and DRAM devices meet, causing errors-especially as speeds increase.

Until now, server designers have had to choose between limiting memory density to reduce high-speed errors or accepting slower speed to achieve high density. With the introduction of FBDIMMs, designers get a no-compromise memory solution that increases reliability, speed, and density.

user posted image

Fully Buffered DIMMs (FBDIMMs) extend memory capacity
>New advanced channel features vastly improve performance
>FBDIMMs are the cost-effective, high-speed, high-density system memory solution for servers, workstations, networking equipment, and high-end desktop computers

What is an " AMB" or Advanced Memory Buffer ?

Fully Buffered DIMMs uses an "Advanced Memory Buffer" chips that maintains signal integrity and improved error detection methods that reduce soft errors make fully buffered DIMMs an ideal system memory solution. Using a point-to-point architecture, the advanced memory buffer (AMB) transmits signals among the controller, memory devices, and other modules without sacrificing signal integrity-or speed. Unlike modules with a parallel path (stub-bus) architecture, FBDIMMs move data serially between the AMB and memory controller.

user posted image

Their simplified structure means FBDIMMs boast a lower pin count and faster transmission rates compared to conventional architectures. Plus, they can perform reads and writes simultaneously, eliminating the read-to-read delay between data transfers. With speeds up to 4.8 Gb/s, FBDIMMs enable fast buffering that optimizes server performance.

With improved Error Detection capabilities , Fully Buffered DIMM are build with features to prevent Address/command soft errors which can disrupt server performance and reliability. To help lessen their occurrence, FBDIMMs incorporate an enhanced cyclic redundancy check (CRC) that provides greater data and address/command protection than traditional server modules.

Designers can also configure it to suit their particular applications. Providing an even greater defense, the bit lane fail-over correction feature identifies bad data paths and removes them from the operation. Together, these error detection methods dramatically reduce address/command soft errors.

FB-DIMM Memory Architecture
The FB-DIMM technology direct signaling interface between the memory controller and the DRAM chips is split into two independent signaling interfaces with a buffer between them. The interface between the buffer and DRAM chips is the same as today, supporting DDR2 (DDR stands for double data rate, a type of SDRAM memory; DDR2 is the second generation) in early FB-DIMM platforms and DDR3 in the future. However, the interface between the memory controller and the buffer is changed from a shared parallel interface to a point-to-point serial interface (see the figure below).

user posted image

The buffer is referred to as the AMB (advanced memory buffer) and a number of suppliers, including Intel, are already making these. The AMB is designed to only take action in response to memory controller commands. The AMB is expected to deliver DRAM commands from the memory controller over the FB-DIMM interface without any alteration to the DRAM devices over the parallel DDR-based interface.

The end result is impressive scalability and throughput: FB-DIMM technology offers scalability of 192 gigabytes - 6 channels, 8 DIMMs/channel, 2 ranks/DIMM, 1 gigabyte DRAMs and offers bandwidth of 6.7 gigabytes per second (GBps) sustained data throughput per channel.

Improving Board Layouts
The FB-DIMM channel pin count is approximately 69 pins per channel, compared with about 240 pins for today's parallel channel. This results in less routing complexity and less routing area between the memory controller and DIMMs (Figures 3 and 4), thereby saving board cost to system manufacturers. For small factor systems such as 1U and blade systems, board real estate is in short supply, and the savings represented by the FB-DIMM technology transition are significant.

user posted image
Figure 3. DDR2 Registered DIMMs: 1 Channel, 2 Routing Layers with 3rd layer required for power Figure 4. FB-DIMMs: 2 Channels, 2 Routing Layers (includes power delivery)

Reliability Now Built In
FB-DIMM technology offers better RAS (reliability, availability, serviceability) by extending the currently available ECC (error check code, a method of checking the integrity of data in DRAM) to include protection of commands and address data. Additionally, FB-DIMM technology automatically retries when an error is detected, allowing for uninterrupted operation in case of transient errors.

Built-in Headroom for the Future
Since the FB-DIMM interface is based on serial differential signaling (similar to Serial ATA, Serial SCSI, PCI Express, and others), a memory controller can support multiple generations of FB-DIMM technology-based components. Today's platforms can support backward compatibility of memory devices (for example, both DDR and DDR2), extending the choice to on-site memory replacements and increasing system flexibility for IT environments. Bottom line, with FB-DIMM systems, an end user could have the flexibility of using first-generation FB-DIMMs with DDR2 DRAM or second-generation FB-DIMMs with DDR3 DRAM.

Reduced Total Cost of Ownership
FB-DIMM technology delivers better TCO (total cost of ownership) to IT in a number of ways: Compatibility of FB-DIMMs across generations means that IT can extend the overall lifespan of DIMM investment through field swapping of DIMMs for new systems. Over time, IT will be able to use a newer generation of DIMMs for better performance or cost.


Due to headroom on capacity and bandwidth and Gen-X compatibility, IT can have more flexibility to repurpose a system for compute-intensive, data-intensive, or I/O-intensive applications, thereby providing better flexibility and range in reprovisioning.

With unprecedented RAS features on memory interfaces such as CRC (cyclical redundancy check) protection on address, retry, bit lane fail-over, hot add while active, and so on, IT would have fewer reasons to bring down the system, resulting in reduced down-time. Because FB-DIMM technology is transparent to OSes and applications, there are no significant barriers to adoption-or realizing-the benefits of the new technology.

Status of FB-DIMM Technology
The FB-DIMM technology standard is currently being authored within the JEDEC Solid State Technology Association industry standards body (www.jedec.org). Interested readers can contact JEDEC directly for the latest status and access to industry standard specifications.

The memory industry has announced broad support of FB-DIMM components in time for the expected launch of FB-DIMM-enabled platforms in the first half of 2006. Intel has been working closely with the industry on FB-DIMM product support plans and is also working with industry tools vendors to ensure a healthy industry ecosystem of enabling tools and programs to fuel industry development.

Intel also founded the Memory Implementers Forum, an industry group cosponsored by Dell, Hewlett-Packard, and IBM, with a mission of accelerating industry development of memory technologies such as FB-DIMM for support of Intel® architecture platforms. More information regarding this forum can be found at www.memforum.com

Source : http://www.simmtester.com/page/news/showpubnews.asp?num=113

This post has been edited by jinaun: Feb 3 2006, 05:49 PM
TomatomanzSeedlezz
post Feb 15 2006, 02:59 AM

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Good info there.. btw, did i miss anything abt "1-sided / 2-sided" rams?.. does it makes a diffs?... unsure.gif

Cheers smile.gif
Viewer
post Mar 4 2006, 09:50 AM

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Er... 1-sided RAM means that you can only find a number of chips (usually 4 or 8) on a side of the DIMM module but none on the other side. 2-sided RAM means that there are chips on both sides.

For DIMM module, 1-sided RAM means that it'll occupy 1 memory bank on your motherboard's RAM slot, while 2-sided RAM occupy 2 memory banks. However, 1 DIMM module (no matter 1 or 2-sided RAM) uses up 1 RAM slot on your mobo.

The differences between "1-sided / 2-sided" rams are as follow:
1) 1-sided RAM usually has denser capacity compare to 2-sided RAM (eg. 512MB RAM = 64Mx8 on 1-sided RAM = 32Mx16 on 2-sided RAM)
2) 1-sided RAM usually has higher latency compare to 2-sided RAM, due to larger capacity. (Those premium RAM usually comes in 2-sided RAM)
3) 1-sided RAM is harder to manufacture, due to larger capacity
4) 1-sided RAM use up less memory banks on your mobo. Some mobos cannot support 8 memory banks, which means that you can't use 4 2-sided RAM at once.

I guess that's about 1-sided/2-sided RAMs
TomatomanzSeedlezz
post Mar 13 2006, 07:53 AM

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Viewer : aaa.. finally a reply.. lol... thx for the info man... the only thing the shopdudes told me its like "1-sided?.. 2-sided?..ooo.. that one ah.. its do with compatibility.. new wan 2-sided".. sweat.gif... its like better dont ask.. tongue.gif..heh

Cheers cool.gif

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