QUOTE(charge-n-go @ Dec 3 2005, 09:59 AM)
lol, i was so blur to notice last nite
btw,
i'm using a NAND b NAND l3 at 1st, but the NAND syntax doesnt allow me to do so, and the compiler asked me to put into bracket form.thanx for your long feedback
anyway, i think my de morgan should be ok (pls refer to the diagram attached). I've tested with a set of input and it is identical to the original AND-OR. Maybe i should try your method as quoted above
Hmm... how about building custom gate with vhdl
maybe i'll js define NAND3 component with this function:
output <= NOT (x AND y AND z);
well, fishy, we not only celebrate here if u win, but oso in the pizza
from the bold sentence, this is due to the fact maxplus 2 doesn't have NAND3
it only has NAND2
theoratically(based on the actual standard), it should be supported......but u know, they done this to suite their hardware requirement, that's why sometimes people prefer to use hdl designer and modelsim to do their simulation because these tools are created to support the standard(and not like Altera etc which build the software to support their hardware)
building custom gates? i don't think it's possible with vhdl........unless they allow you to do UDP(User Defined Primitives) which so far MaxPlus2 isn't supported(and i think vhdl doesn't have these, only Verilog as far as i know)
QUOTE(charge-n-go @ Dec 3 2005, 10:51 AM)
btw, wat is "Quin-McClusky", hahaha.
Here is the comparison of this design and the mux approach.
better alternative to k-map
but i always use multisim to simplify my design(yah, i'm lazy), that software uses QM method
QUOTE(martianunlimited @ Dec 3 2005, 11:36 AM)
Quine McCluskey (I can never spell that properly, hence i keep using the name QM) is a reduction technique to reduce the logic to a SOP (sum of products). QM gives most benefit when you are dealing with a lot of outputs (eg. BCD convertor, LCD interface), otherwise K-Map would be easier (i suggested QM because you have 6 inputs, and it's not easy to build a 6 input K-Map)
http://en.wikipedia.org/wiki/Quine-McCluskey_algorithm(Using QM on my digital clock circuit got me a A+ for "digital logic and design")
(i didn't know that there was a 2 digit decimal->BCD then a BCD->LCD convertor and i actually did a 6 bit binary number -> LCD (14 outputs.. VERY painful to reduce... (especially for the LCD for the first digit)
actually, QM is more suited for odd number variable, if it's even number, k-map is easier, but no matter what, it's not as accurate as QM(k-map needs more practice to grasp the correct method, while QM is tedious, but more easier to pick up and highly accurate)
p/s: anyone modelled a RAM using Verilog b4? mine seems to have problem(minor delay when combined with the controller)
dual-port RAM
CODE
module ram_test4(data_out, data_in, r_add, w_add, clk, write_en, read_en);
output[5:0] data_out; //data output for read signal
input[5:0] r_add, w_add; //read and write address
input[5:0] data_in; //data input to be written to RAM
input clk, write_en, read_en; //enable write option
reg[5:0] mem[35:1];
assign data_out = read_en? mem[r_add]:5'bz;
always@(posedge write_en)
begin
if(write_en)
mem[w_add]<=data_in;
else
mem[w_add]<=mem[w_add];
end
endmodule
write controller
CODE
module write_control3(en_write1, en_write2, w_add, clk, reset, en);
output[5:0] w_add;
output en_write1, en_write2;
input clk, reset, en;
reg[6:0] count;
reg[5:0] w_add;
reg en_write1, en_write2;
always@(posedge reset or posedge clk)
begin
if(reset)
count<=7'b0;
else if(~en)
count <= count;
else if(count<35 && en==1)
count <= count + 1;
else if(count<70 && en==1)
count <= count + 1;
else if(count>69 && en==1)
count <= 7'b1;
end
always@(en or clk)
begin
if(count<36)
begin
w_add <= count[5:0];
en_write1 <= en;
en_write2 <= 1'b0;
end
else if(count<71)
begin
w_add <= count[5:0]-35;
en_write1 <= 1'b0;
en_write2 <= en;
end
end
endmodule
read control
CODE
module read_control2(en_read1, en_read2, r_add, clk, reset, en);
output[5:0] r_add;
output en_read1, en_read2;
input clk, reset, en;
reg[6:0] count;
reg[5:0] r_add;
reg en_read1, en_read2;
always@(posedge reset or posedge clk)
begin
if(reset)
count<=7'b0;
else if(~en)
begin
count <= count;
en_read1 <= 1'b0;
en_read2 <= 1'b0;
end
else if(count<35 && en==1)
begin
count <= count + 1;
en_read1 <= 1'b1;
en_read2 <= 1'b0;
end
else if(count<70 && en==1)
begin
count <= count + 1;
en_read1 <= 1'b0;
en_read2 <= 1'b1;
end
else if(count>69 && en==1)
count <= 7'b1;
end
always@(en)
begin
if(count<36)
begin
r_add <= 36 - count[5:0];
end
else if(count<71)
begin
r_add <= 71 - count[5:0];
end
end
endmodule
problem with the simulation is that it supposed to store data 0-34
but upon reading out the data, it stored 1-35
i was wondering if there's a solution to it
This post has been edited by X10A Freedom: Dec 3 2005, 11:07 PM 
Oct 12 2005, 09:43 PM
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