some mask layout images from my final year project, i know it sux , so just bear with it


ever seen a butterfly mask layout?


the whole viterbi decoder:


This post has been edited by X10A Freedom: Mar 31 2006, 07:24 PM

i think he's just purely lazy(with a little artsy)
it could have been more compact if the components on the right hand side were as compact as the left hand side

defintely can since HDLs are meant to be portable to any platform that supports it
but expect the result to be different from wat u did on MaxPlus2
it maybe faster, or slower

normally the codes are synthesizable no matter what, it's just that the result of the synthesis may be different(gonna be bigger in size or so? depends)
therefore people use 3rd party software to do simulation and synthesis(mentor, synopsis etc) so that the end result doesn't varies for different cpld/fpga

p/s: aren't u supposed to be sleeping too much coffee or so? XD

This post has been edited by X10A Freedom: Apr 3 2006, 03:40 PM

studying at kbu, the butterfly section is not done by me
it's using mentor graphics ic flow, i use my school's pc to capture the screen as such tools aren't available as freely as Altera products

dun bother searching for lanun especially in LYP, it's pretty futile
u can try the great intr@n3t though
if u do find one, care to share with me too XD
jobs after graduation......hmm, that's something i'm hoping for but things aren't going to smoothly though
already missed one interview from altera
but they might be coming back, so keeping my fingers cross
anyways, anyone here have any knowledge on mentor graphics boardstation(aka EN2004 which includes Accusim, Design Architect etc) tools? i need to verify something about that especially things regarding LVS

This post has been edited by X10A Freedom: Apr 3 2006, 08:51 PM

well, i need to know how to setup the Design Architect so that i can do LVS with the mask layout
i need to confirm that my college is lacking of something that stops me from doing this

well, when i was attempting the questions, i haven't really learn layouts in detail yet(they only gave me like few days just to prepare )
after they processed the answers for the questions(which took quite long), i've mostly done on my layout, but too bad, i wasn't call up for the interview(though some of my classmates did but only 2-3 person in total was really confirmed after the interview)
but my lect was telling me that the ic design department might want to go for a 2nd round recruitment.......so i'm hoping that this time, i'm well prepare for it

add another signal
RESULT : STD_LOGIC_VECTOR (15 DOWNTO 0);

reg <= result[15..8];


i think should be written this way
or else it will be
reg <= result[15 downto 8];

by shifting it, u won't get the data that u want as the addition will not be the same anymore
1 clk cycle means the cycle in relative to the clk, it's not instruction dependant, unlike microcontrollers which uses 1 clk for each instructions

ok, then update 'reg' outside of the clk event(after the end process statement)
it should save u 1 clk cycle

depending on synthesis tools, most A+B function doesn't need any clock at all(that boils down to what u intend this to do, a counter? or an adder?)
so the remainding clk cycle is waste on add_result <= A+B
the reason i say remove the

reg <= add_result( 15 downto 8)

and put it at outside is so that u won't incur another clk cycle just to tap a signal bus and pass it to an output
but putting outside of the process statement, it means tapping of the internal signal to the specified output
wierd.....it should work since

add_result <= A+B;

so by just putting this code

reg <= add_result( 15 downto 8);

at outside of the process statement will meant that you are tapping the 15 downto 8 bus to 'reg'

its the same as clk
clk is just train of pulses and the register updates at every pulse
normally when we refer to update according to clk, we meant that the registers are edge triggerred circuits

no, i meant registers in general
there aren't any registers that consist of latch though(dun count in pulsed latch) which are level sensitive circuits

neat mask layout
i really need to brush up my skill to your level
= /

w00t, congrats

balance between hardware and software? but most topic that u suggest are more towards software side or can be done purely by software

i'm not sure about topics 1 & 2, but i think topic 2 is more to dsp since equalizations are related to filters in the first place
topic 3....i'm quite sure is purely software, just can't recall wat software they are using, will get back to u on this
topic 4 can be done using labview or matlab
topic 5 is can be done using java, my college last time did some that are related to security or parking ticket

FPGA outpacing ASIC? more like more companies are embracing FPGA due to it's rapid prototyping(which cuts a lot of cost compare to prototyping an ASIC which a single mask layout already cost an atom bomb(j/k )
it'll never be mainstream especially it's current structure, and also not to forget certain disadvantage like not being able to do programmable analogue mixed signal(but i heard there is already a programmable analogue device, think it was called FPAA)

FPGA are never meant to be competitive at all, it's speed already puts it in some disadvantages, not to mention cost and utilizations etc
so, it's not bad being a "fanboy" of an ASIC , coz i believe it still rules in terms of catering for the mass market(even catering for 1 million clients is still consider niche in the current industrial standard


no, not low volume, it's Xtremely low volume........but ISDN cards were like stoneage compare to current DSL, so i would suspect that during then, the embracement towards ASIC were a little lukewarm(especially ISDN since the response it received was lukewarm too )

This post has been edited by X10A Freedom: Jul 14 2006, 11:03 AM

lol, are those papers available to us legally?

err, not cut away(if can do it without making a new mask, please tell me, i'll split the earnings with you )
just think of it as a FPGA but with lesser programmability

p/s: oi, seems like u're damn free, no work to do?

i'll answer y u go to Singapore instead of Penang
coz Altera penang dun really focus much of their energy on FPGA
i'm sure Halo is aware of this too

This post has been edited by X10A Freedom: Nov 21 2006, 08:27 PM