35 = 100011 which is 6-bit
i never meant to access address 0
that's why i put my ram depth [35:1]
unless putting it that way still make the first address 000000
i'll check and see if the first address is still 000000, but that could be the problem though
the problem is that i need to run the counter till 70
the first 35 to store the first set of data, the subsequent to store the 2nd set
any ideas of making the controller easier other than the things u suggested?

This post has been edited by X10A Freedom: Dec 4 2005, 01:20 PM

gray code?! nah, i need the data in sequence and i don't need to make my design any complicated again, gotta rush this behavioral coding to structural one as i think i'm running out of time
it's not said so in the question paper though(coz there's no question paper at all XD)
it's the requirement of my viterbi decoder
it's 35 because the decoder will process data every 35 time frames and each time frame it'll need to store a value that was processed within a certain section, hence accumulating 35 values after 35 times frames for the other section to process the data

anyways, memory depth is power 2 of wat? i didn't knew there were such restriction/criteria

anyways, i've already solve the problem, seems like it's due to the clock edge not being able to detect the first data, therefore i synchronize the data input with the write controller

haha, that's not really creating a UDP(User Defined Primitive) coz the transistor count is different (3 input NAND has 6 transistor while 3 input AND with NOT will have 8)
maybe u should at least try Quartus 2 or HDL designer & Modelsim, it's better than Maxplus2

This post has been edited by X10A Freedom: Dec 4 2005, 04:59 PM

forgive my crapiness in electrical field, but your connection on the capacitor seems wierd.......
and why put so many of those capcitors in series? since when do we need so many capacitors to act as a filter?(unless this is some industrial transformer )
and if you want an answer, please show us your working first b4 demanding one, or else don't expect to get one
anyways, if the connection of the capacitor is such, then i would say your answer is wrong
and to know why? look more info on transformer, u forgot about the current value(since when secondary voltage is equal to the load voltage? )

This post has been edited by X10A Freedom: Dec 10 2005, 09:33 PM

i don't care it's a homework or not
but when u want to know whether your answer is correct or wrong, u should show the working first so that people who are knowledgeable in this field can tell u what when wrong in your analysis(if there's any).
based on your previous posts, u just keep on demanding an answer, is that call learning to you? even if it's not a homework, u should also have the same attitude in analysing the circuit, not demanding one
anyways, seeing such "attitude" from you, the more i won't want to waste my time flipping my notes to tell you the answer(since i suck in electrical as i told you, still need to flip through my notes)
and i already gave you a slight hint to solve the problem, but u decide to ignore it, too bad then(but then, my analysis can be wrong too )

hmm, wat am i major in? i also don't know
probably digital ASIC design since my FYP is on that

image processing, sounds like a final year project a few groups in my college that are doing.......don't tell you me are one of them

This post has been edited by X10A Freedom: Dec 31 2005, 12:11 AM

it's the same as people asking what is the application of VHDL
anyways, it's basically the same as VHDL which is to model Digital Systems (ASIC etc)
but advantageous of verilog over vhdl? more back end friendly
which means it's easier for softwares to synthesize it to physical form compare to VHDL(since VHDL is quite an abstract language)

This post has been edited by X10A Freedom: Jan 13 2006, 09:26 PM

anyone can recommend me a software that can do transistor timing simulation(other than Orcad PSPICE or AccuSim 2)





p/s: but if u have the AccuSim 2 software, please PM me

anybody use transmission gates for specific gate operations(xor, mux etc) ?
just wondering, in transistor schematic simulation, did u all place buffers at the input of the transmission gates to avoid it feedbacking the signal back to the input?

This post has been edited by X10A Freedom: Feb 21 2006, 10:34 PM

hmm, let's say u form a Xor gate using transmission gates
and if u don't put buffers at the inputs
can u're circuit still run? the simulator at my college is giving me lots of headaches
if i can use transmission gates, it'll greatly reduce my transistor counts

using Design Architect bar the analogue library(apparently my college can't determine which analogue library we should use, so we have to use the digital nmos/pmos library)
the problem is, without putting a buffer at the input, the software apparently assume that the signal at the output of the transmission gate will feedback some signal to the input which in the end render the transmission gate not attractive anymore if i always need to put a buffer just to prevent the signal from feedbacking

yes, i know transmission gates are bidirectional
but the let's say i supply 1 at point A
and it suppose to flow out at point B when the switch is open
but, in the end the signal at point B flow to point A which is pretty ridiculous as voltage potential flow from high to low, not low to high
sigh, hope my college can quickly solve the software issue on the analogue simulator

most of the times, certain operations are embedded into the fpga's lut
so when u use behavioral instead of structural, it gives the software more flexibility when synthesizing it into the real hardware

it still utilizes lut's and muxes to do the work
muxes are good stuffs in terms of implementing arithmetic and sequential devices

just wondering, is it possible to have a via that connects from metal 2 or 3 straight to the polysilicon?
coz currently it needs to be done in a ladder form

ya, that's wat i'm doing now, but i was hoping to be able to make a via straight down to the poly from any metal layer
i'm doing the layout for the memory section of the viterbi decoder
trying to use only metal 1 but it's quite difficult to maintain it at metal 1

any useful links or books on mask layout?
i seriously need one though my fyp due date is soon
poly is evil? y eh? my lecturer told me otherwise
actually, i did try doing my layout using multiple layers of metals and use lesser poly
but the result isn't good as in the end all my metals is on top of my gates which i think it isn't good especially thermal dissipation

yah, first time doing layout
not doing SRAM, only latches(though i wanted to use pulsed latch, but the analogue library and the simulator came a bit too late as my project due date is soon)
SRAM needs a precharge circuit which i for one can't find any info about it

thanks for the advice

This post has been edited by X10A Freedom: Mar 10 2006, 10:22 PM

i'm not sure about the design rules(i'm drawing based on lamda method instead of micron method), how to check eh?
i think there isn't any restriction to metal layer though i would prefer to maintain it at 3-4 layers

not for the lambda in IC design rule
i just realise my ic design rule is from MOSIS

u put my memory in to shame