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 Asus A | U | N series combined thread V2, New model coming in.....

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kizwan
post Nov 1 2010, 12:01 AM

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QUOTE(budingyun @ Oct 31 2010, 10:42 PM)
slot 1 is stock ram..

slot 2 also stock ram from my friend notebook..

i trade my new 2gb kingston 1066mhz with his stock 2gb kingston 1333mhz..
*
I got a question about your CPU-Z screenshot. Did you run HWiNFO32 program before running CPU-Z?

This post has been edited by kizwan: Nov 1 2010, 12:02 AM
kizwan
post Nov 1 2010, 09:11 AM

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QUOTE(budingyun @ Nov 1 2010, 08:26 AM)
no...

this is latest version of CPUZ 1.56..

HWiNFO32 only needed for CPUZ 1.55 and older i think..

because with latest version of CPUZ the the RAM information always show..
*
Yes, you're right. I thought I was using latest CPU-Z.
kizwan
post Nov 1 2010, 09:23 AM

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QUOTE(verdangilte @ Nov 1 2010, 09:17 AM)
which one come with original another is purchase few weeks ago
*
Don't forget to update your signature. LOL

I also found out that if you put 2GB DDR3-1333 & 2GB DDR3-1066, it still work in dual-channel mode.
kizwan
post Nov 1 2010, 10:07 AM

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QUOTE(verdangilte @ Nov 1 2010, 09:51 AM)
lol  i forget jor tiam ...tongue.gif

erm why u dun wan use same 1333mhz ??
*
I'm on holiday @ kampung right now. The only DDR3 module I can find is 2GB DDR3-1066. Since our i5 only utilize 1066 so I just bought it. The funny story is when I ask for 2GB DDR3-1333, she said DDR3-1333 is only for desktop pc not for notebook. LOL.

(P/S: The reason why CPU-Z v1.55 & older doesn't detect the memory SPD information is because the "hidden" SMBUS controller (I use word "missing" earlier). It only got detected after we run HWiNFO32 program. I think I can fix it but I'm too lazy to do it. Maybe later. tongue.gif )

This post has been edited by kizwan: Nov 1 2010, 10:12 AM
kizwan
post Nov 4 2010, 02:35 PM

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To A42JV owner, look what appeared on my A42JV Device Manager. The "missing/hidden" SMBUS controller is now visible. tongue.gif
Attached Image
kizwan
post Nov 4 2010, 06:37 PM

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QUOTE(Amal @ Nov 4 2010, 06:10 PM)
Tried DDR 1066. IT WORKS!
Last time I tried 1333.

Phew.. The RAM is slower, but I won't mind as long as I can get 8GB to do my work!  biggrin.gif
*
Maybe the DDR3 1333 module is faulty. If it is not, I recommend you to call Asus support.
kizwan
post Nov 4 2010, 07:29 PM

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QUOTE(Amal @ Nov 4 2010, 07:09 PM)
Already emailed to their support... no response...
Yeah, they do that. laugh.gif Are you using the Technical Inquiry page at Asus member/support page? They will respond to you, don't worry about it (maybe after a week laugh.gif ). Remember to follow up with Asus support/Royal Club since your A42JA should support DDR3 1333 since it have i7 processor which utilize it (chipset PM55 & HM55 already support DDR3 1333).


Added on November 4, 2010, 7:59 pm
QUOTE(RedDevils88 @ Nov 4 2010, 07:12 PM)
mine is not visible.. but what does it do?
(Source)
The System Management Bus (abbreviated to SMBus or SMB) is a single-ended simple two-wire bus for the purpose of lightweight communication. Most commonly it is found in computer motherboards for communication with the power source for ON/OFF instructions.
It is derived from I²C for communication with low-bandwidth devices on a motherboard, especially power related chips such as a laptop's rechargeable battery subsystem (see Smart Battery Data). Other devices might include temperature, fan or voltage sensors, lid switches and clock chips. PCI add-in cards may connect to a SMBus segment.

I believe the "missing/hidden" SMBUS controller is the reason why SPD information is not visible with CPU-Z v1.55 because it can't communicate with SMBUS controller. It only displayed after we launch HWiNFO32 Program. Newer version, CPU-Z v1.56, able to scan & communicate with the "missing/hidden" SMBUS controller without any third party program. The same way HWiNFO32 Program & Everest (beta version) can scan/detect the "missing/hidden" SMBUS controller.

The SMBUS controller only appear on Device Manager after I inject it in ACPI table (DSDT). I currently dual-boot with Mac OS X (purely for experiment & research). When using Mac OS X you need to use modified DSDT just like linux on unsupported computer. This is what I inject in the DSDT:-
CODE

       Device (SBUS) // Intel SMBus Controller
       {
           Name (_ADR, 0x001F0003)
           OperationRegion (SMBP, PCI_Config, 0x40, 0xC0)
           Field (SMBP, DWordAcc, NoLock, Preserve)
           {
                   ,   2,
               I2CE,   1
           }
           OperationRegion (SMPB, PCI_Config, 0x20, 0x04)
           Field (SMPB, DWordAcc, NoLock, Preserve)
           {
                   ,   5,
               SBAR,   11
           }
           OperationRegion (SMBE, PCI_Config, 0x04, 0x02)
           Field (SMBE, AnyAcc, NoLock, Preserve)
           {
               IOSE,   1                       // I/O Space Enable
           }
           OperationRegion (SMBI, SystemIO, ShiftLeft (SBAR, 0x05), 0x10)
           Field (SMBI, ByteAcc, NoLock, Preserve)
           {
               HSTS,   8,                      // Host Status
                       Offset (0x02),
               HCON,   8,                      // Host Control
               HCOM,   8,                      // Host Command
               TXSA,   8,                      // Transmit Slave Address
               DAT0,   8,                      // Host Data Byte 0
               DAT1,   8,                      // Host Data Byte 1
               HBDR,   8,                      // Host Block Data
               PECR,   8,                      // Packet Error Check
               RXSA,   8,                      // Receive Slave Address
               SDAT,   16                      // Receive Slave Data
           }
           Name (SBOK, Zero)
           Method (ENAB, 0, NotSerialized)     // Enable Method
           {
               Store (One, IOSE)
               Store (One, SBOK)
           }
           Method (DISB, 0, NotSerialized)     // Disable Method
           {
               Store (Zero, SBOK)
           }
           Method (SSXB, 2, Serialized)        // SMBus Send Byte(Arg0:Address, Arg1:Data)
           {
               If (STRT ())                    // Is the SMBus Controller Ready?
               {
                   Return (Zero)               // Failure
               }
               // Send Byte
               Store (Zero, I2CE)              // SMBus Enable
               Store (0xBF, HSTS)
               Store (Arg0, TXSA)              // Write Address
               Store (Arg1, HCOM)              // Write Data
               Store (0x48, HCON)              // Start + Byte Data Protocol
               If (COMP ())                    // Check if last operation completed
               {
                   Or (HSTS, 0xFF, HSTS)       // Clean up
                   Return (One)                // Success
               }
               Return (Zero)                   // Failure
           }
           Method (SRXB, 1, Serialized)        // SMBus Receive Byte(Arg0:Address, Return:0xffff=Failure, Data (8bit)=Success)
           {
               If (STRT ())                    // Is the SMBus Controller Ready?
               {
                   Return (0xFFFF)
               }
               // Receive Byte
               Store (Zero, I2CE)              // SMBus Enable
               Store (0xBF, HSTS)
               Store (Or (Arg0, One), TXSA)    // Write Address
               Store (0x44, HCON)              // Start
               If (COMP ())                    // Check if last operation completed
               {
                   Or (HSTS, 0xFF, HSTS)       // Clean up
                   Return (DAT0)               // Success
               }
               Return (0xFFFF)
           }
           Method (SWRB, 3, Serialized)        // SMBus Write Byte
           {
               If (STRT ())                    // Is the SMBus Controller Ready?
               {
                   Return (Zero)               // Failure
               }
               Store (Zero, I2CE)              // SMBus Enable
               Store (0xBF, HSTS)
               Store (Arg0, TXSA)              // Write Address
               Store (Arg1, HCOM)              // Write Command
               Store (Arg2, DAT0)              // Write Data
               Store (0x48, HCON)              // Start + Byte Protocol
               If (COMP ())                    // Check if last operation completed
               {
                   Or (HSTS, 0xFF, HSTS)       // Clean up
                   Return (One)                // Success
               }
               Return (Zero)                   // Failure
           }
           Method (SRDB, 2, Serialized)        // SMBus Read Byte(Arg0:Address,Arg1:Command, Return:0xffff=Failure, Data (8bit)=Success)
           {
               If (STRT ())                    // Is the SMBus Controller Ready?
               {
                   Return (0xFFFF)
               }
               Store (Zero, I2CE)              // SMBus Enable
               Store (0xBF, HSTS)
               Store (Or (Arg0, One), TXSA)    // Write Address
               Store (Arg1, HCOM)              // Write Command
               Store (0x48, HCON)              // Start + Byte Protocol
               If (COMP ())                    // Check if last operation completed
               {
                   Or (HSTS, 0xFF, HSTS)       // Clean up
                   Return (DAT0)               // Success
               }
               Return (0xFFFF)
           }
           Method (SWRW, 3, Serialized)
           {
               If (STRT ())
               {
                   Return (Zero)
               }
               Store (Zero, I2CE)
               Store (0xBF, HSTS)
               Store (Arg0, TXSA)
               Store (Arg1, HCOM)
               And (Arg2, 0xFF, DAT1)
               And (ShiftRight (Arg2, 0x08), 0xFF, DAT0)
               Store (0x4C, HCON)
               If (COMP ())
               {
                   Or (HSTS, 0xFF, HSTS)
                   Return (One)
               }
               Return (Zero)
           }
           Method (SRDW, 2, Serialized)
           {
               If (STRT ())
               {
                   Return (0xFFFF)
               }
               Store (Zero, I2CE)
               Store (0xBF, HSTS)
               Store (Or (Arg0, One), TXSA)
               Store (Arg1, HCOM)
               Store (0x4C, HCON)
               If (COMP ())
               {
                   Or (HSTS, 0xFF, HSTS)
                   Return (Or (ShiftLeft (DAT0, 0x08), DAT1))
               }
               Return (Ones)
           }
           Method (SBLW, 4, Serialized)        // Single Bit Line Write?
           {
               If (STRT ())                    // Is the SMBus Controller Ready?
               {
                   Return (Zero)               // Failure
               }
               Store (Arg3, I2CE)
               Store (0xBF, HSTS)
               Store (Arg0, TXSA)
               Store (Arg1, HCOM)              // Write Command
               Store (SizeOf (Arg2), DAT0)
               Store (Zero, Local1)
               Store (DerefOf (Index (Arg2, Zero)), HBDR)
               Store (0x54, HCON)
               While (LGreater (SizeOf (Arg2), Local1))
               {
                   Store (0x0FA0, Local0)
                   While (LAnd (LNot (And (HSTS, 0x80)), Local0))
                   {
                       Decrement (Local0)
                       Stall (0x32)
                   }
                   If (LNot (Local0))
                   {
                       KILL ()
                       Return (Zero)
                   }
                   Store (0x80, HSTS)
                   Increment (Local1)
                   If (LGreater (SizeOf (Arg2), Local1))
                   {
                       Store (DerefOf (Index (Arg2, Local1)), HBDR)
                   }
               }
               If (COMP ())                    // Check if last operation completed
               {
                   Or (HSTS, 0xFF, HSTS)       // Clean up
                   Return (One)                // Success
               }
               Return (Zero)                   // Failure
           }
           Method (SBLR, 3, Serialized)        // Single Bit Line Read?
           {
               Name (TBUF, Buffer (0x0100) {})
               If (STRT ())
               {
                   Return (Zero)
               }
               Store (Arg2, I2CE)
               Store (0xBF, HSTS)
               Store (Or (Arg0, One), TXSA)
               Store (Arg1, HCOM)
               Store (0x54, HCON)
               Store (0x0FA0, Local0)
               While (LAnd (LNot (And (HSTS, 0x80)), Local0))
               {
                   Decrement (Local0)
                   Stall (0x32)
               }
               If (LNot (Local0))
               {
                   KILL ()
                   Return (Zero)
               }
               Store (DAT0, Index (TBUF, Zero))
               Store (0x80, HSTS)
               Store (One, Local1)
               While (LLess (Local1, DerefOf (Index (TBUF, Zero))))
               {
                   Store (0x0FA0, Local0)
                   While (LAnd (LNot (And (HSTS, 0x80)), Local0))
                   {
                       Decrement (Local0)
                       Stall (0x32)
                   }
                   If (LNot (Local0))
                   {
                       KILL ()
                       Return (Zero)
                   }
                   Store (HBDR, Index (TBUF, Local1))
                   Store (0x80, HSTS)
                   Increment (Local1)
               }
               If (COMP ())
               {
                   Or (HSTS, 0xFF, HSTS)
                   Return (TBUF)
               }
               Return (Zero)
           }
           Method (STRT, 0, Serialized)        // Wait for SMBus to become ready
           {
               Store (0xC8, Local0)            // Timeout 200ms
               While (Local0)
               {
                   If (And (HSTS, 0x40))       // IN_USE?
                   {
                       Decrement (Local0)
                       Sleep (One)                   // Wait 1ms
                       If (LEqual (Local0, Zero))    // timeout--
                       {
                           Return (One)
                       }
                   }
                   Else
                   {
                       Store (Zero, Local0)    // We're ready
                   }
               }
               Store (0x0FA0, Local0)          // Timeout 200ms (50us * 4000)
               While (Local0)
               {
                   If (And (HSTS, One))        // Host Busy?
                   {
                       Decrement (Local0)
                       Stall (0x32)                  // Wait 50us
                       If (LEqual (Local0, Zero))
                       {
                           KILL ()
                       }
                   }
                   Else
                   {
                       Return (Zero)           // Success
                   }
               }
               Return (One)                    // Failure
           }
           Method (COMP, 0, Serialized)        // Check if last operation completed
           {
               Store (0x0FA0, Local0)          // Timeout 200ms in 50us steps
               While (Local0)
               {
                   If (And (HSTS, 0x02))       // Completion Status?
                   {
                       Return (One)            // Operation Completed
                   }
                   Else
                   {
                       Decrement (Local0)
                       Stall (0x32)
                       If (LEqual (Local0, Zero))
                       {
                           KILL ()
                       }
                   }
               }
               Return (Zero)                   // Failure
           }
           Method (KILL, 0, Serialized)        // Kill all SMBus communication
           {
               Or (HCON, 0x02, HCON)           // Send Kill
               Or (HSTS, 0xFF, HSTS)           // Clean Status
           }
           Device (BUS0)
           {
               Name (_CID, "smbus")
               Name (_ADR, Zero)
               Device (DVL0)
               {
                   Name (_ADR, 0x57)
                   Name (_CID, "diagsvault")
                   Method (_DSM, 4, NotSerialized)
                   {
                       Store (Package (0x03)
                       {
                           "address",
                           0x57,
                           Buffer (One)
                           {
                               Zero
                           }
                       }, Local0)
                       DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                       Return (Local0)
                   }
               }
           }
       }

Even though I was injecting it only on Mac OS X, somehow it enable or unhidden the SMBUS controller. When boot to windows it got detected & windows installed the appropriate driver.

It is not a problem but usually it is visible in Device Manager. This show us that A42JV BIOS have buggy ACPI.

This post has been edited by kizwan: Nov 4 2010, 07:59 PM
kizwan
post Nov 4 2010, 11:53 PM

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QUOTE(eugenechiuu @ Nov 4 2010, 10:30 PM)
Oo.. How's mac osx's compability on a42jv? Battery life longer?
*
Still working on graphic card detection. No hardware acceleration yet.
kizwan
post Nov 5 2010, 12:41 AM

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QUOTE(lee_what2004 @ Nov 5 2010, 12:01 AM)
Could it be the reason for the higher discharge rate as well?
*
Maybe...

Please look here. Someone with K52J notebook (with Optimus) disabled the Nvidia GPU on linux to save battery. It does drop the battery drain rate.

In our (A42JV) DSDT, I can see \_SB.PCI0.PEG1.GFX0.DOFF & \_SB.PCI0.PEG1.GFX0.DON (ON/OFF Nvidia GPU). So, you can call it manually using the acpi_call tool.


This post has been edited by kizwan: Nov 5 2010, 12:45 AM
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post Nov 5 2010, 01:04 AM

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QUOTE(lee_what2004 @ Nov 5 2010, 12:43 AM)
I tried to disable the GT335M on device manager, but ended up with higher discharge rate, -20W instead of -12W in idle....
*
I think it just disabled the software/driver from accessing it. It may still drawing power. If we can figure out how to make ACPI call on windows (\_SB.PCI0.PEG1.GFX0.DOFF - turn off the Nvidia GPU), I think we can improve the battery life.
kizwan
post Nov 6 2010, 02:43 PM

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QUOTE(eugenechiuu @ Nov 6 2010, 09:50 AM)
Hmm.. I tried installing iDeneb but it doesnt boot at all and keep restarting... What's the prob? Is it due to my missing SMBUS controller thingy?
*
No, it is due to compatibility issue with the processor. This is not appropriate forum to discuss about this. Anyway, I do not recommend you to install it yet because you will be disappointed. I will let you know when our notebook is supported.

BTW, please buy original installer DVD. It is not too expensive compared to windows.

This post has been edited by kizwan: Nov 6 2010, 02:45 PM
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post Nov 7 2010, 12:54 PM

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QUOTE(budingyun @ Nov 7 2010, 09:37 AM)
wow you so lucky to get A42JV stock  biggrin.gif
*
What do you mean? You didn't got stock/original A42JV? Why is that?

This post has been edited by kizwan: Nov 7 2010, 12:54 PM
kizwan
post Nov 7 2010, 01:09 PM

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Oh! I see. laugh.gif
kizwan
post Nov 7 2010, 03:32 PM

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QUOTE(erszebeth @ Nov 7 2010, 03:22 PM)
now, back to the qtion, i know 5730 outrun 5650 just by a lil bit, but as an overall performance of notebook (4820tg n a42ja), is it differ so much...?

as for the i7 in asus, nvr use intel 'i' tech b4... still using c2d atm, how does the i7 open it's other core...? auto or we ctrl it manually...? or depends on certain program...?
*
Based on overall performance, A42JA will have better performance compared to 4820TG. But since A42JA have i7 quad core processor, you should know the idle temp will be 5+ celcius. Are you OK with that?

It will be auto. Can't control it manually. It will depend on processor temperature & TDP (thermal design power) (I only remember two).


Added on November 7, 2010, 3:43 pm
QUOTE(erszebeth @ Nov 7 2010, 03:22 PM)
i cant say that im a heavy gamer, but i do play games like, 7 8 hours a day... be it online games or not...
Since you did mention this, I want to recommend you to get Alienware M11x notebook instead. It still under your price range, under 4k.
EDIT: Sorry, URL linking doesn't work. You can visit Dell website for more information.

This post has been edited by kizwan: Nov 7 2010, 03:47 PM
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post Nov 7 2010, 05:13 PM

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QUOTE(erszebeth @ Nov 7 2010, 04:29 PM)
kizwan, i would really consider the alienware...the cpu it uses im afraid will cause a bottleneck for the overall performance.. uhuh...
Yeah, the screen will be too small but CPU won't cause bottleneck.

Last time (2 month ago) I tried to find 4820TG with 5650 but only found 5470. Anyway, I didn't look hard enough.
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post Nov 7 2010, 05:43 PM

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How about Acer Aspire 5942G? It have 5650 - RM3999.
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post Nov 7 2010, 05:52 PM

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Ops! My mistake.
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post Nov 11 2010, 12:29 AM

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QUOTE(mimi89 @ Nov 11 2010, 12:14 AM)
just now i tried to install ubuntu 10.10, the ubuntu worked fine now.

However i tin i choose wrong option during installation and deleted my window 7.

If I use a crack window 7, will it void my warranty?
*
I don't think software, including windows, are covered under warranty. Parts only.


Added on November 11, 2010, 12:30 am
QUOTE(ScivanShimitar @ Nov 11 2010, 12:15 AM)
yeah even the cooler
*
Your hard disk is kaput I think. Try remove the hard disk.

This post has been edited by kizwan: Nov 11 2010, 12:30 AM
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post Nov 11 2010, 11:59 AM

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QUOTE(ScivanShimitar @ Nov 11 2010, 07:22 AM)
Well i dunno,
the hard disk does make alot of twitching sound on the bootscreen when I was booting
My hard disk is silence while at boot screen. A42JV will paused at the boot screen while it tries to detect/initialize the CD (if loaded) & external drive (if connected). It may also true while it try to initialize the hard disk. I don't think it is motherboard or BIOS problem because, usually, if it is, you should already see error messages on the screen.

*boot screen = Asus splash screen

This post has been edited by kizwan: Nov 11 2010, 12:00 PM
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post Nov 13 2010, 04:12 AM

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QUOTE(drumhitz @ Nov 13 2010, 03:49 AM)
hi guys... jz bought a A42JC with Nvidia Geforce 310M.... but somehow, i think my laptop is not running on nvidia, it is all the while running on Intel HD Graphics card (integrated)...

i hav tried to use CPU-Z and under Graphics, i cant even select at the Display Device Selection...

Is this the usual case???
*
Yes, by default it will run on Intel HD. Nvidia will only be use when it needed by applications, for example playing games. Open Nvidia Control Panel, go to View menu & select "Display GPU Activity Icon in Notification Area". In Program Settings tab, set Windows Media Player to use Nvidia. Play a movie/video. At the same time point your mouse pointer to "red-green" icon at Notification area (at taskbar - right-bottom), click on the icon (not double-click). You'll see Windows Media Player icon under GPU Activity. If you can see it, that means your Nvidia is in use.

CPU-Z can't detect the Nvidia GPU properly. Sometime it detect it (usually while an application use Nvidia) & sometime it don't.

Yes, this is usual case.

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