

http://pc.watch.impress.co.jp/docs/2007/1204/kaigai404.htm
those who can read japs... pls translate...
lol
R700 overview, take with a grain of salt first..
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Dec 4 2007, 11:03 PM, updated 19y ago
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#1
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Elite
6,139 posts Joined: Jan 2003 |
![]() ![]() http://pc.watch.impress.co.jp/docs/2007/1204/kaigai404.htm those who can read japs... pls translate... lol |
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Dec 4 2007, 11:04 PM
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#2
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Elite
6,139 posts Joined: Jan 2003 |
from the pix.. i'm assuming.. there is no more texture/etc/etc duplication in memory when running on XFire
This post has been edited by jinaun: Dec 4 2007, 11:05 PM |
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Dec 4 2007, 11:11 PM
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64 posts Joined: Oct 2006 |
how come the japs got the news earlier? wheres the americans?
anyway r700 will be dual core huh? This post has been edited by En.Vader: Dec 4 2007, 11:12 PM |
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Dec 4 2007, 11:15 PM
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#4
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Elite
6,139 posts Joined: Jan 2003 |
QUOTE(En.Vader @ Dec 4 2007, 11:11 PM) its known r700 hav to be multicore oledi.. think of it as xfire on a stick.. its not feasible to make a single gpu with the target performance at current manufacturing technology. |
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Dec 4 2007, 11:30 PM
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Senior Member
4,251 posts Joined: Jan 2003 From: Malacca, Malaysia, Earth |
QUOTE(jinaun @ Dec 4 2007, 11:15 PM) its known r700 hav to be multicore oledi.. think of it as xfire on a stick.. But isn't GPU already a massively parallel processor? I mean, if you can put in multiple core on the same die (you must be able to cramp that much transistor on a die) why not come up with an architecture that has twice the SMP in one single coreits not feasible to make a single gpu with the target performance at current manufacturing technology. I may be wrong but I finds multicore on GPU to be very strange.. ps: I'm not doubting the source. Just unsure of the benefits ATi sees in making multi core GPU. Furthermore, what is the architecture? is it new, or are they just slapping in the same old architecture with smaller fabrication process and so cramping 2 cores on one die. |
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Dec 4 2007, 11:44 PM
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#6
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Elite
6,139 posts Joined: Jan 2003 |
QUOTE(Hornet @ Dec 4 2007, 11:30 PM) But isn't GPU already a massively parallel processor? I mean, if you can put in multiple core on the same die (you must be able to cramp that much transistor on a die) why not come up with an architecture that has twice the SMP in one single core well.. i don't know whether they put multiple core into 1 gpu or a single board comprising of multiple smaller gpusI may be wrong but I finds multicore on GPU to be very strange.. ps: I'm not doubting the source. Just unsure of the benefits ATi sees in making multi core GPU. Furthermore, what is the architecture? is it new, or are they just slapping in the same old architecture with smaller fabrication process and so cramping 2 cores on one die. and.. to get more performance, you need to cram more transistor in the single die.. which currently we are hitting 700mill for 8800GT. i think its cheaper to manufacture smaller gpu compared to a single large gpu. well.. its not entirely new, but i'm sure its based on R600 and new improvements incorporated to enable it to reach the target performance required for R700 |
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Dec 4 2007, 11:50 PM
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1,251 posts Joined: Jul 2006 From: Petaling Jaya |
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Dec 5 2007, 04:52 AM
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10,544 posts Joined: Jan 2003 From: GMT +8:00 |
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Dec 5 2007, 10:01 PM
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#9
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875 posts Joined: Oct 2004 From: Selayang, Selangor |
The transition of the GPU core is moving dramastically in next year. Looking forward to hearing from this in next year.
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Dec 5 2007, 11:09 PM
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962 posts Joined: Dec 2004 From: Kulai |
QUOTE(jinaun @ Dec 4 2007, 11:04 PM) from the pix.. i'm assuming.. there is no more texture/etc/etc duplication in memory when running on XFire if it's true, then its good news indeed, because currently dual chip boards such as x1650xt gemini from sapphire have 2 sets of memory one for each gpu but basically both sets of memory holds the same data and this makes it redundant and it finally leads to an increase in production cost and pcb complexity thus increasing the price This post has been edited by ben_panced: Dec 5 2007, 11:10 PM |
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Dec 6 2007, 10:11 AM
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2,659 posts Joined: Sep 2006 From: Miri, PJ & KL |
View it as integrated cores...you know, like how Intel slapped 2 C2D to make a single C2Q. The integration have integrated memory controller that allows sharing of memory and is able to turn off a single core when working on desktop applications such as Office or the like. This is a replication of CPU architecture...but not sure if it's real or not.
Yes, GPU is already massively parallel. Just think of this as integrated Crossfire or something like that. No need for bridge, better buses, etc. Don't rely on this much though. I don't work with AMD.ATI, but I don't think this is where they are heading for R700...then again, I may be wrong. |
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Dec 6 2007, 11:25 AM
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10,544 posts Joined: Jan 2003 From: GMT +8:00 |
QUOTE(clayclws @ Dec 5 2007, 09:11 PM) View it as integrated cores...you know, like how Intel slapped 2 C2D to make a single C2Q. The integration have integrated memory controller that allows sharing of memory and is able to turn off a single core when working on desktop applications such as Office or the like. This is a replication of CPU architecture...but not sure if it's real or not. It's not like a single dual core cpu sharing a single memory controller, because that would give them no benefit. It's more likely to have chips with independent memory controllers and nonoverlapping address spaces, like amd chips connected via hypertransport. It's an improved crossfire.Yes, GPU is already massively parallel. Just think of this as integrated Crossfire or something like that. No need for bridge, better buses, etc. Don't rely on this much though. I don't work with AMD.ATI, but I don't think this is where they are heading for R700...then again, I may be wrong. |
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Dec 6 2007, 11:38 AM
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381 posts Joined: Jun 2007 From: イチゴ軍団 |
SIMPLE TRANSLATIONS:
First Title: Planned/ speculation of Future High-End GPU trend Dual-die GPU: Mostly saying that the die will be half the size of now high-end GPUs, shared memory with lower latency, high bandwidth interconnection between MCM GPUs and thus lowering task processing overhead, blah blah... Second Title: Power saving method on Dual-die GPU Left Pic: High load Right Pic: Low load |
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Dec 6 2007, 11:45 AM
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2,659 posts Joined: Sep 2006 From: Miri, PJ & KL |
QUOTE(ikanayam @ Dec 6 2007, 11:25 AM) It's not like a single dual core cpu sharing a single memory controller, because that would give them no benefit. It's more likely to have chips with independent memory controllers and nonoverlapping address spaces, like amd chips connected via hypertransport. It's an improved crossfire. Yes, exactly what I'm trying to say. This post has been edited by clayclws: Dec 6 2007, 11:48 AM |
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Dec 6 2007, 11:57 AM
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10,544 posts Joined: Jan 2003 From: GMT +8:00 |
QUOTE(clayclws @ Dec 5 2007, 10:45 PM) Yes, exactly what I'm trying to say. Let's just say, by the time the merger came about, R700 was well on its way already. AMD will have no influence on the designs till maybe the R800 or later generation. And i'm not saying it will use hypertransport, i'm just saying it's a similar configuration to amd chips using hypertransport. It probably will use a different connection method. |
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Dec 6 2007, 12:03 PM
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1,966 posts Joined: Jan 2003 From: No longer hanging by a NUS |
QUOTE well.. i don't know whether they put multiple core into 1 gpu or a single board comprising of multiple smaller gpus and.. to get more performance, you need to cram more transistor in the single die.. which currently we are hitting 700mill for 8800GT. i think its cheaper to manufacture smaller gpu compared to a single large gpu. The diagram states its Multi Chip Module (MCM) so it's multiple dies (perhaps even > 2 ?) on a single substrate. Most likely will be connected via Hypertransport. It will be cheaper to manufacture the dies but slightly harder to assemble. QUOTE(ikanayam @ Dec 6 2007, 11:25 AM) It's not like a single dual core cpu sharing a single memory controller, because that would give them no benefit. It's more likely to have chips with independent memory controllers and nonoverlapping address spaces, like amd chips connected via hypertransport. It's an improved crossfire. I believe Larabee is going to have multiple in-order x86 cores with separate L2 caches all attached to a larger shared memory: kind of like how C2D have a shared last level cache (LLC). |
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Dec 6 2007, 12:13 PM
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Senior Member
2,659 posts Joined: Sep 2006 From: Miri, PJ & KL |
QUOTE(ikanayam @ Dec 6 2007, 11:57 AM) Let's just say, by the time the merger came about, R700 was well on its way already. AMD will have no influence on the designs till maybe the R800 or later generation. And i'm not saying it will use hypertransport, i'm just saying it's a similar configuration to amd chips using hypertransport. It probably will use a different connection method. Wow, you seemed well informed. It seems logical though, since AMD themselves announced that their merger will only bear real fruit towards the end of 2008 and starting of 2009. Should be R800 or maybe RV7xx or something like that.Added on December 6, 2007, 12:13 pmAnyway, let's just hope for the best for AMD.ATI. We need competition in all areas. This post has been edited by clayclws: Dec 6 2007, 12:13 PM |
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Dec 6 2007, 12:21 PM
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10,544 posts Joined: Jan 2003 From: GMT +8:00 |
QUOTE(cks2k2 @ Dec 5 2007, 11:03 PM) The diagram states its Multi Chip Module (MCM) so it's multiple dies (perhaps even > 2 ?) on a single substrate. Most likely will be connected via Hypertransport. It will be cheaper to manufacture the dies but slightly harder to assemble. CPUs are different, and i'm not expecting Larabee to be an out of this world GPU performer either. It will probably be "good enough" at the most for true GPU apps except maybe some triangle setup limited cases. They're probably going to market it as more of a gpgpu part and for "raytracing". And current GPUs are already multicore (have been for a while), with hundreds of threads per core. The problem is going multichip and getting good scaling.I believe Larabee is going to have multiple in-order x86 cores with separate L2 caches all attached to a larger shared memory: kind of like how C2D have a shared last level cache (LLC). |
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Dec 6 2007, 01:05 PM
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2,275 posts Joined: Jan 2007 From: 192.168.200.45 |
Dual cores have existed awhile...i agree...the the dram sharing is it new?
And whats with the multi chip module? noob in this |
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Dec 6 2007, 02:07 PM
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2,659 posts Joined: Sep 2006 From: Miri, PJ & KL |
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