tahniah sudah naik pangkat G5.

wow. let me guess.

AMD
Lattice
Oppstar

all offer so high >7k for G5 equivalent 🤔 fantasy1989 true or not?

as to your original question. currently Intel is not in a good financial position. they are focusing more to get their foundry business going, so a lot money to spend. since you are on the design FE side, should join fabless IC design company as they has higher profit margin and hence can offer higher salary.

yes, in a startup you get to learn a lot more. in MNC like Intel, you tend to be confined to your small domain of work only. if want to explore, need to show yourself to manager and volunteer but this depends. for person that need to be pushed, then join startup better as you get to explore more stuff as your deliverables ie you are forced to learn more than volunteer to do so.

regarding wfh or office. no comment. up to individuals.

This post has been edited by ipohps3: Jun 21 2024, 11:00 PM

Thanks! Hope I get the enthusiasm to keep up and promoted or lompat to better company

You go with what till tiring. Me everyday 10-15 minutes only for 10km.

should lompat liao. around 3 years can jump to get higher increment.

Drive - last time always 6am leave condo - stuck in Relau/Sg Ara - Lim Chong Eu or
Pantai Hospital - Jalan Tengah - Airport route highway for 45 mins.

Just to be in PG15 office before crowd come lo.

Then 4.30pm early cabut. Otherwise another nightmare jam again.
Again I don't like driving, it is quite stressful for me to be on the road. Penang motorcycles also...


Otherwise, nowadays, I sit on Intel's Home Shuttle, 6.30am head down, feed mosquito in open air for 15-30 minutes, shuttle pick up others around 20-30 mins. Then be in PG12 at 7.30am, quick settle breakfast in new cafe, then catch 8am Shuttle PG12 to PG16, clock in at 8.20am-ish, walk back to my cube edi 8.30am.

Then to end of the day, ride 3.30pm / 4pm back to PG12, wait until next shuttle 5pm comes or sit RapidPenang walk 20mins / Grab back to my condo at Relau. Then continue OT work to monitor simulation and collapse on bed...

And the tedious cycle repeats.

I just want jump to other companies to find someone willing to guide or teach under a proper mentorship to properly learn Analog/Digital IC Design.

Here everyday do flow related issues troubleshooting/debugging/reporting.
Not much in terms of actual Design Use or guidance.

Everyone's here an individual contributor only

KEK i daily ride motor back and forth. At most 20minutes only if really jam and only when go back home.

8.30am leave house. Go for breakfast. 9.00am++ reach bayan lepas FTZ

This post has been edited by kesvani: Jun 22 2024, 12:04 AM

I don't have a motor license.
and Penang Motorcycle Drivers really i kennot.

If company can offer more flexible working arrangement, and more easy peaceful ways to commute to work.
Surely will increase my affinity / morale to go work.

I guess digital will be easier. If analog, most of them are veterans, if not you either have masters.

Need to have strong fundamentals, like circuit theory, control system, etc.

Most of the time digital/analog design, they will be using back old RTL for digital and circuit topology for analog. Even the sizing for analog circuit have been set and sometimes you just adjust according to process node. For digital, you just make minor improvements to the RTL I guess? You don’t reinvent the wheel every generation of processors.

What do you current job scope? Interesting?

I don't have masters.

I gotten into Intel as G.T. as some weird title "Functional Validation Engineer" at an Electrical Validation team. Last time do Electrical Validation and System Margin Validation, everyday test 3-5 test chip, sweep code on software variables, Process (slow/fast chip), Voltage, Temperature., find recipe / optimized for biggest eye diagram, debug design, or find ways to improve workflow and productivity by reducing Test Report generation.

After 1 year, my contract ending, ask my connection from my Fabless IC Design colleague who jump into Intel, whether her team hiring.

I didn't really have strong fundamentals in Analog IC Design, I just jump in to help out testing new Methodology and Flows, and just work in running simple simulations for Digitals Blocks. I can recognized Op-Amps, Band Gaps reference circuits, but to design and optimize - abit not my cup of tea since everyone so busy and not really much guidance. So eventually just carry on this Analog title, doing other things.

Which sometimes I quite worry I'm in my comfort zone too long.

This post has been edited by iSean: Jun 22 2024, 11:12 AM

7k is the benchmark for design engineer 2 level outside of Intel. Of course it also depends on how you do during technical interview and how bold are you in selling yourself. One thing I realized is Malaysian interviewers are more cincai. AMD has 2 stage interviews, first stage from local team. 2nd stage from China team. This is because the AMD team in Penang reports to China team who leads the design of Ryzen's IO die and IPs. The Malaysian interviewer usually just ask what you do and ask you elaborate from there. China interviewer will tend to drill down on technical details more.

AMD still got design team in China? I thought since US vs China tech war, AMD should have gotten out from there? especially for design team. also this 7k is for those Master freshgrad or with prior experience?

This post has been edited by ipohps3: Jun 22 2024, 06:16 PM

in a startup, even new freshgrad got the chance to design ie code RTL from ground up, base on customer requirements. you learn a lot more. I believe those ground breaking IP design in Intel is still given priority to Israel or US design team. Intel Malaysia design team design team mainly doing SoC integration and validation.

hence joining those startups either local or China will be greatly beneficial. no such thing as make minor improvements to RTL.

This post has been edited by ipohps3: Jun 22 2024, 06:37 PM

@ipohps3

Yes AMD still have design team in China. Intel also still have design team in China. But obviously they don't handle critical compute IPs. China team is handling the Northbridge and Southbridge dies just like how Intel Malaysia handles the PCH die.

7k is with prior experience. The range of salaries between Intel and others in Penang are roughly as follows:

Intel GT - RM4k |Others fresh grad / design engineer 1 - RM5k - RM6k
Intel G3 - RM4.5k |Others fresh grad / design engineer 1 - RM5k - RM6k
Intel G5 - RM5k - RM6k |Others Design Engineer 2 - RM7k
Intel G6 - > RM7k ish |Others Sr Design Engineer - RM 8.5k - >9k ish

Note this is for Front End RTL Design / Verification work.

This post has been edited by Xflkekw: Jun 22 2024, 09:52 PM

Even startup in Malaysia don't do "ground breaking IP design". A lot of them are licensed from other IP vendors like Synopsys.

Our design ecosystem is still mainly focused on IOs related IP (Your PCIE, USB, SATA, Ethernet, JESD, Interlaken, FPGA fabric interconnect etc). That is Penang's expertise (Thanks to Intel). Even the design teams starting up at AMD and Lattice are focusing on IOs. You can even take a look at Skyechip's product, they dont actually design compute cores themselves. They are licensing Arm IPs for that.

Eh I would say Intel Malaysia does a lot more than just SoC integration and validation. We have IP design, verification, SoC design, integration and verification, Analog IPs, SoC structural design, Atom core design (very small team) and Atom core validation, Tools & Design Enablement & methodology team, compute tile structural design and firmware & software teams. There are probably more that I missed out and this is just for the Intel client product side not accounting for PSG / Altera teams.

In terms of RTL design workloads, I don't think your statement is entirely true. You can have the opportunity to make a lot of RTL changes or design some functionality from scratch too at Intel. Large IP teams like PCIE subsystem usually provide that opportunity. Even at other local /China startup you are mostly likely making design changes on IP licensed from other Vendors like Synopsys / Arm instead of designing it from the ground up yourself.

some companies has Engineer 3 role before Senior Engineer. not sure how that will affect the salary range.

This post has been edited by ipohps3: Jun 23 2024, 12:02 AM

WFH in the morning, till like 10am only go in lah. Traffic will be much better

You’re in Analog Design department but mostly doing mostly related issues troubleshooting/debugging/reporting?