If Intel 1 year, no convert, how nice your team is, also no point they unable to convert you as Perm-BB.

If you gotten offered from Altera/PSG. Better stay away, as already news broke Altera/PSG is going standalone.

Another problem is Intel, you might be working in your bubble too often.
Don't really deal with other teams much unless you are needed to. Eventually you get too comfortable with your job and can't really progress.

If you like me, think already hit rock bottom in terms of learning. I think better you avoid this company.

Also you might need to try to understand what type of Jobs are there in VLSI. Can be verification, pre-Si, post-Si, RTL, Layout, Physical Design, Place and Route, Analog IC Design, Digital IC design, IC Standard Cell library, Board Design, Electrical Validation, etc...
GT (1 year - 2021) - RM 4k
Grade 3 (2 years -2022/23)- GT + 6%
Grade 5 (3 months)- RM 5.2k
Anyhow, see what team you are in, some are good, some are bad, some are really under pressured until you can mentally cracked at times.

Ayam Intel Grade 5 too. Got offers from A, L and O recently for Design Engineer 2 (Grade 5 equivalent). All over 7k. Intel fucking underpaying. If not for the fact I live in Alor Setar and only need to go office once every week or even once every two weeks, I would have jumped lel

Thanks! Hope I get the enthusiasm to keep up and promoted or lompat to better company 

7k is the benchmark for design engineer 2 level outside of Intel. Of course it also depends on how you do during technical interview and how bold are you in selling yourself. One thing I realized is Malaysian interviewers are more cincai. AMD has 2 stage interviews, first stage from local team. 2nd stage from China team. This is because the AMD team in Penang reports to China team who leads the design of Ryzen's IO die and IPs. The Malaysian interviewer usually just ask what you do and ask you elaborate from there. China interviewer will tend to drill down on technical details more.

I guess digital will be easier. If analog, most of them are veterans, if not you either have masters.

Need to have strong fundamentals, like circuit theory, control system, etc.

Most of the time digital/analog design, they will be using back old RTL for digital and circuit topology for analog. Even the sizing for analog circuit have been set and sometimes you just adjust according to process node. For digital, you just make minor improvements to the RTL I guess? You don’t reinvent the wheel every generation of processors.

What do you current job scope? Interesting?

@ipohps3

Yes AMD still have design team in China. Intel also still have design team in China. But obviously they don't handle critical compute IPs. China team is handling the Northbridge and Southbridge dies just like how Intel Malaysia handles the PCH die.

7k is with prior experience. The range of salaries between Intel and others in Penang are roughly as follows:

Intel GT - RM4k                      |Others fresh grad / design engineer 1 - RM5k - RM6k
Intel G3 - RM4.5k                  |Others fresh grad / design engineer 1 - RM5k - RM6k
Intel G5 - RM5k - RM6k          |Others Design Engineer 2 - RM7k
Intel G6 - > RM7k ish              |Others Sr Design Engineer - RM 8.5k - >9k ish

Note this is for Front End RTL Design / Verification work.

Even the design teams starting up at AMD and Lattice are focusing on IOs.
Expected. US MNC will normally give sensitive IP to US team.

You can even take a look at Skyechip's product, they dont actually design compute cores themselves. They are licensing Arm IPs for that.
From what I know, Skypechip is venturing in VIP which is almost like IP.

Eh I would say Intel Malaysia does a lot more than just SoC integration and validation. We have IP design, verification, SoC design, integration and verification,
yes

Analog IPs, SoC structural design,
Not FE as in FE of the FE before structural/physical design.

Atom core design (very small team) and Atom core validation,
this I know people working on it. mostly adopting previous big core IP.

Tools & Design Enablement & methodology team, compute tile structural design and firmware & software teams.
Not digital design that I referring to.

In terms of RTL design workloads, I don't think your statement is entirely true. You can have the opportunity to make a lot of RTL changes or design some functionality from scratch too at Intel. Large IP teams like PCIE subsystem usually provide that opportunity.
This I not sure.

Even at other local /China startup you are mostly likely making design changes on IP licensed from other Vendors like Synopsys / Arm instead of designing it from the ground up yourself.
For the startup that I know in Penang, they do design their CPU IP from the group up (hint: RISCV).

I did not join Intel. The workload in small company is alot more, but the learning you get to experience is a lot. And the bonus is nice too, can get 2-3 months.