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 My TeamGroup TCCD 500Mhz RAM cn't use on DFI RD200, Any solution....

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casperito
post Dec 24 2006, 03:17 AM

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juz got a pair of ddr600 and put it in the yellow slot...
got no problem and still can boot into windows...
but onli can run on 2T timing... 1T cannot boot...
still have to do somemore research on this ram...
casperito
post Dec 24 2006, 07:37 AM

221.133.99.99
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Senior Member
662 posts

Joined: Feb 2006
From: int eth 5/0/16 vlan 13


for tccd user... on ATI chipset mobo...
use the orange slot and try these setting on your mobo...

Genie BIOS Settings:

FSB Bus Frequency............................. - 300
LDT/FSB Frequency Ratio....................... - 4.0
CPU/FSB Frequency Ratio....................... - 9.0
RD580 HT PLL Speed............................ - High Speed
HT Bus MMOS Drive Strength.................... - 05
HT Bus PMOS Drive Strength.................... - 05
HT Bus Receiever Impedance.................... - 05
CPU HT Bus Drive Strength..................... - Normal

CPU VID Control............................... - Auto
CPU VID Special Control....................... - dun remember but set till get 1.6v
DRAM Voltage Control.......................... - 2.80v
SB PCIE Voltage............................... - 1.80v
NB Analog Voltage............................. - 1.34v
LDT Bus Voltage............................... - 1.34v
NB Core Voltage............................... - 1.34v


DRAM Configuration Settings:

DRAM Frequency Set............................ - 200=RAM/FSB:01/01
Command Per Clock (CPC)....................... - Enable
CAS Latency Control (Tcl)..................... - 3.0 Bus Clocks
RAS# to CAS# delay (Trcd)..................... - 04 Bus Clocks
Min RAS# active time (Tras)................... - 08 Bus Clocks
Row precharge time (Trp)...................... - 04 Bus Clocks
Row Cycle time (Trc).......................... - 10 Bus Clocks
Row refresh cyc time (Trfc)................... - 16 Bus Clocks
Row to Row delay (Trrd)....................... - 03 Bus Clocks
Write recovery time (Twr)..................... - 03 Bus Clocks
Write to Read delay (Twtr).................... - 02 Bus Clocks
Read to Write delay (Trwt).................... - 03 Bus Clocks
Refresh Period (Tref)......................... - 1560 Cycles
DRAM Bank Interleave.......................... - Enabled
Errata 94 Enhancement......................... - Disable
Errata 123 Enhancement........................ - Auto
Odd Divisor Correct........................... - Disable

DQS Skew Control.............................. - Auto
DQS Skew Value................................ - 0
DRAM Drive Strength........................... - Level 3
DRAM Data Drive Strength...................... - Level 1
DIMM 1/3 Clock Timing Skew.................... - Auto
DIMM 2/4 Clock Timing Skew.................... - Delay 450
Max Async Latency............................. - 8.0 ns
Read Preamble Time............................ - 5.5 ns
IdleCycle Limit............................... - 64 Cycles
Dynamic Counter............................... - Disable
R/W Queue Bypass.............................. - 16 x
Bypass Max.................................... - 4 x
Burst Length.................................. - 4 Bursts


you can try to adjust the FSB... but the DRAM setting juz keep it the way it is...

this setting is mainly for CFX3200 user...

juz Oced my x2 to 2.7ghz...
will try to prime later on...

got help from other overseas OCer that use the same spec as me

casperito
post Dec 25 2006, 01:29 AM

221.133.99.99
****
Senior Member
662 posts

Joined: Feb 2006
From: int eth 5/0/16 vlan 13


update....
the setting is still not stable...

 

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