sorry noob here
how to know that processor and motherboard is ivy bridge ??

okay thanks for telling
but I can't find in intel website
can provide the link ?
how about laptop ?? any idea ?

thanks for the link
any news when they release for desktop and laptop ?
or already release, sorry really noob here
can't tahan to wait the ivy bridge release to buy either desktop or laptop ><

LOL i also kena sudden shock in the morning. Took a chill pill trying to calm myself to ignore the readings as my fingers still feel cool when touching both the rads, CPU block, tubing as well as the res. there was no hot air dissipated out of the rads. So i found:
Ivy Bridge Temperatures Could Be Linked To TIM Inside Integrated Heatspreader: Report

32 phases looks juicy 
but how does it take on MVE? 

Binning 163x i7 3770K !!!
http://hwbot.org/forum/showthread.php?t=58161

DDR3-3040 

There's no NB since Sandy Bridge.

yes, there's no more uncore clock since Sandy
Look at CPU-Z, NB frequency reading is removed from the Memory tab.
Ivy:

Nahelem: (apologize the image is too small)

I'm not sure how does L3 cache relate to core clock.
IMC doesn't accelerate or move.. it is just a mem controller thus no clock

With Nehalem Intel introduced an on-die L3 cache behind a smaller, low latency private L2 cache. At the time, Intel maintained two separate clock domains for the CPU (core + uncore) and a third for what was, at the time, an off-die integrated graphics core. The core clock referred to the CPU cores, while the uncore clock controlled the speed of the L3 cache. Intel believed that its L3 cache wasn't incredibly latency sensitive and could run at a lower frequency and burn less power. Core CPU performance typically mattered more to most workloads than L3 cache performance, so Intel was ok with the tradeoff.

In Sandy Bridge, Intel revised its beliefs and moved to a single clock domain for the core and uncore, while keeping a separate clock for the now on-die processor graphics core. Intel now felt that race to sleep was a better philosophy for dealing with the L3 cache and it would rather keep things simple by running everything at the same frequency. Obviously there are performance benefits, but there was one major downside: with the CPU cores and L3 cache running in lockstep, there was concern over what would happen if the GPU ever needed to access the L3 cache while the CPU (and thus L3 cache) was in a low frequency state. The options were either to force the CPU and L3 cache into a higher frequency state together, or to keep the L3 cache at a low frequency even when it was in demand to prevent waking up the CPU cores. Ivy Bridge saw the addition of a small graphics L3 cache to mitigate this situation, but ultimately giving the on-die GPU independent access to the big, primary L3 cache without worrying about power concerns was a big issue for the design team.