QUOTE(almostthere @ Nov 29 2007, 11:12 PM)
I can't disagree with you on that but one has to consider the fact what with Intel forging ahead with larger cache at L2 instead of going L3, and at the same time developing tech which negates or reduces the latency associated with large cache, it's hard not to be imginative with what may possibly be achievable once implementation of integration is achieved and if it's inline with what the goals of HTT 2.0 are, we may see greater bandwidth being made available altho by right current microproc designs being churned out by Intel aren't that memory hungry (Correct me if I'm wrong, getting forgetful nowadays). And with that, it's possible a substantial if not leapfrogging evolution of micro-p architecture at consumer market level. As for Northwood, I can't personally agree it's a failure since it did serve it's purpose well eventhough it close to it's design limitation. Prescott and subsequently Cedar Mill should be the one's to be considered the real flops as Intel chose to prolong a design which was fast running into a performance-per-watt wall. IINM, Cedar Mill's heat density scaled to the point that at an equivalent one sqaure meter, it generated enough waste heat equivalent to a small power plant (Thanks to ikanayam for pointing out that fact last time).
As for Bloomfield, from what I heard from the grapevine, that seems to be a stop-gap measure although I can't get nor divulge any further details since it's unsubstantiated and/or it's based on the trust as friends
Intel is going the L3 route. I've seen rough design schematics (Gainestown) and making informed guesses the L2 is exclusive and smaller with a shared L3: it's almost Barcelona like.
QUOTE(X.E.D @ Nov 30 2007, 07:34 AM)
Was talking on Northwood at Hyperthreading level.
Its HTT implementation was utterly useless.
Nehalem could be designed with H-T in mind, and that's where I'm betting on Intel for that boost AMD can't have in synthetics (after all, synthetics are EVERYTHING in CPUs, no way bypassing them in performance assessments)
Bloomfield could be a stopgap, but that would be counting on 32nm to be implemented quickly and to get Sandy Bay out fast. Which would be rather ideal as these chips are huge.
Actually HyperThreading was designed for P4 except it was disabled on the Wilamette core IIRC (or at least that's what the Intel senior engineers tell us).