Welcome Guest ( Log In | Register )

Bump Topic Topic Closed RSS Feed

Outline · [ Standard ] · Linear+

 Phenom x3 and x4 now in Malaysia, The new K10

views
     
cks2k2
post Nov 19 2007, 11:09 PM

...
******
Senior Member
1,966 posts

Joined: Jan 2003
From: No longer hanging by a NUS

Phenomenal failure is more like it.
Compare Phenom to a Penryn and the lead becomes even bigger.
Surprisingly a bug was discovered so late into production that they couldn't produce a stable 2.4 GHz model (some TLB thingy).

I'm waiting for X.E.D. to give his take...
cks2k2
post Nov 21 2007, 09:15 AM

...
******
Senior Member
1,966 posts

Joined: Jan 2003
From: No longer hanging by a NUS

QUOTE(masterpyan @ Nov 21 2007, 08:49 AM)
Not sure why everyone is hyped up over Fusion - it's just a mainstream GPU sharing the same die with the CPU. Don't expect super-1337 performance from the integrated GPU, a discrete part will still pwn it. Same goes for Nehalem's integrated GPU: it'll still get pwned by discrete parts. (last time I looked Nehalem's GPU is on a separate die but in same pkg -> MCM)

QUOTE
No, it means that no other processor maker other then intel can produce x86 if there is no AMD

VIA has an x86 license.

This post has been edited by cks2k2: Nov 21 2007, 09:17 AM
cks2k2
post Nov 21 2007, 08:47 PM

...
******
Senior Member
1,966 posts

Joined: Jan 2003
From: No longer hanging by a NUS

QUOTE(Fields @ Nov 21 2007, 08:19 PM)
wonder why ibm does not market their own x86 procs....they will totally pawn!
*
At 1 point in time they did but they couldn't do it economically well enough (read: lose money) so they gave up.
x86 is pretty much an Intel vs AMD thing with VIA being a spectator. IBM prefers to just do research and license the IP.

The one who has the performance crown dictates the pricing game: Intel is literally choking AMD to death by forcing them to sell their procs at a loss. HUge die + bad yields + poor performance = loss.
cks2k2
post Nov 22 2007, 01:24 PM

...
******
Senior Member
1,966 posts

Joined: Jan 2003
From: No longer hanging by a NUS

QUOTE(Laguna @ Nov 22 2007, 12:56 PM)
Amd phenom price has been release

Phenom 9600 (2.3GHz, 95W, 2MB total dedicated L2 cache, 2MB L3 cache, 3600MHz HyperTransport(tm) bus, socket AM2+) 

Price $283
Phenom 9500 (2.2GHz, 95W, 2MB total dedicated L2 cache, 2MB L3 cache, 3600MHz HyperTransport(tm) bus, socket AM2+)

Price $251
*
Is that in 1000 units or retail?

QUOTE(ncool15 @ Nov 22 2007, 01:16 PM)
Phenom's retail packaging.

user posted image user posted image user posted image

More pictures here:

http://infomars.fr/forum/index.php?showtopic=1052
*
The artwork is pretty good but the cooler looks el cheapo.
cks2k2
post Nov 29 2007, 02:20 PM

...
******
Senior Member
1,966 posts

Joined: Jan 2003
From: No longer hanging by a NUS

QUOTE(ikanayam @ Nov 29 2007, 01:09 PM)
5-10% hit. Of course the sources are scarce, i didn't read that on the internets.
*
I thought the errata could cause the system to hang at speeds > 2.4 ?
cks2k2
post Nov 29 2007, 06:26 PM

...
******
Senior Member
1,966 posts

Joined: Jan 2003
From: No longer hanging by a NUS

QUOTE(X.E.D @ Nov 29 2007, 05:43 PM)
K6(-2/3) was quite a competitor on non-performance/brand-name boxes.

But that's essentially... meh.  laugh.gif
*
Hi X.E.D., nice of you to drop by... tongue.gif

Anyway rumor has it there's going to be a Black edition Phenom (unlocked multi).
The marketing/PR people must be running AMD now like Intel during the P4 days:
1. Quadfather aka 4x4 that bombed
2. "40% better"
3. "Pure quad core better than MCM"
4. Black editions
5. "Spider" platform after calling Intel's platform idea "locking the consumer in, depriving them of choice"
6. Controlled benchmarks
7. "We don't paper launch" -> yet no one can get a Barcelona/Phenom

Bring back the engineers!
cks2k2
post Nov 30 2007, 10:48 AM

...
******
Senior Member
1,966 posts

Joined: Jan 2003
From: No longer hanging by a NUS

QUOTE(almostthere @ Nov 29 2007, 11:12 PM)
I can't disagree with you on that but one has to consider the fact what with Intel forging ahead with larger cache at L2 instead of going L3, and at the same time developing tech which negates or reduces the latency associated with large cache, it's hard not to be imginative with what may possibly be achievable once implementation of integration is achieved and if it's inline with what the goals of HTT 2.0 are, we may see greater bandwidth being made available altho by right current microproc designs being churned out by Intel aren't that memory hungry (Correct me if I'm wrong, getting forgetful nowadays). And with that, it's possible a substantial if not leapfrogging evolution of micro-p architecture at consumer market level. As for Northwood, I can't personally agree it's a failure since it did serve it's purpose well eventhough it close to it's design limitation. Prescott and subsequently Cedar Mill should be the one's to be considered the real flops as Intel chose to prolong a design which was fast running into a performance-per-watt wall. IINM, Cedar Mill's heat density scaled to the point that at an equivalent one sqaure meter, it generated enough waste heat equivalent to a small power plant (Thanks to ikanayam for pointing out that fact last time).

As for Bloomfield, from what I heard from the grapevine, that seems to be a stop-gap measure although I can't get nor divulge any further details since it's unsubstantiated and/or it's based on the trust as friends
*
Intel is going the L3 route. I've seen rough design schematics (Gainestown) and making informed guesses the L2 is exclusive and smaller with a shared L3: it's almost Barcelona like. nod.gif

QUOTE(X.E.D @ Nov 30 2007, 07:34 AM)
Was talking on Northwood at Hyperthreading level.
Its HTT implementation was utterly useless.

Nehalem could be designed with H-T in mind, and that's where I'm betting on Intel for that boost AMD can't have in synthetics (after all, synthetics are EVERYTHING in CPUs, no way bypassing them in performance assessments)

Bloomfield could be a stopgap, but that would be counting on 32nm to be implemented quickly and to get Sandy Bay out fast. Which would be rather ideal as these chips are huge.
*
Actually HyperThreading was designed for P4 except it was disabled on the Wilamette core IIRC (or at least that's what the Intel senior engineers tell us).

Topic ClosedOptions
 

Change to:
| Lo-Fi Version
0.0251sec    0.45    7 queries    GZIP Disabled
Time is now: 7th December 2025 - 10:03 AM