One bad spin = technical mistake.
One screwup after another = something wrong with management.

http://chip-architect.com/news/Shanghai_Nehalem.jpg
With 6MB L3, it's going to be around 240mm^2, about the same size as the nehalem. With a 2MB L3 (which is very likely going to be available, looking at the L3 layout), it's going to be around 180mm^2. The 2MB version might have 2 less HTT pads, but that doesn't save much. I don't think there will be 0MB L3 versions because it seems like the L3 is probably an essential part of the memory heirarchy.

The L3 isn't really an issue for clocks. It runs at the memory controller clock, which is much slower than the core clock.

This post has been edited by ikanayam: Mar 16 2008, 10:08 AM

It is extremely unlikely for cache to cause hotspots unless there's a huge problem with the cache design. In which case you probably wouldn't put such a flawed design into production. I think the NB/L3 clocks will have a max speed per cpu generation, they won't directly track core clock increases.

As you have more cores, a unified lower level cache makes sense if the coherence controller is smart enough to use it for data sync between cores. Else all this traffic has to go through memory, which is way way slower. It's not the L3 that's causing them problems. They're having issues with caches in general.

1. There is no L3 TLB. And even if there was, that's a tiny part of the chip, and if they can't manage that then they sure as hell can't manage the L1 and L2 TLB heat density.

2. You don't cut money on such things. You just don't. The investment there is nothing compared to the cost of your fabs and the money you save on a smaller/denser chip. Also, you amortize huge fixed costs over a huge number of chips that you sell. That's the only reason we can afford to buy these things. edit: the reason why they did it is probably because making the cells smaller for the L3 would not have helped them due to their issues with low swing read cells. They are using single ended reads so they needed larger cells for that anyway.

3. The K10 core is basically a K8 core with an extra FPU stuck on the side with more front end bandwidth. So it will likely not have much/any clock headroom over the K8 given the same conditions.

This post has been edited by ikanayam: Mar 16 2008, 03:01 PM

You want to isolate just the CPU when finding the max cpu clock. So adjusting multipliers is the best way to do this, to keep memory from affecting the overclock. If you want to go to extremes, a much less extreme intel overclock will easily smack the phenom anyway so it's pointless either way.

This post has been edited by ikanayam: Apr 4 2008, 11:23 PM

Whomever wrote that article doesn't know what he's talking about. 5GHz links = PCIe 2.
PCIe 3 will use something like 8GHz links.