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 P4 Northwood vs Prescott GUIDE, P4 "C" vs P4 "E"

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charge-n-go
post Apr 9 2004, 01:41 PM

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P4E needs very long pipeline stages in order to ramp up to high clock speed in the future. It also uses larger cache to compensate the long pipeline penalty. Well, it claims that the branch prediction has improved significantly. It's normal for longer pipeline CPU to perform weaker due to the pipeline latency in every stages, if 1 stage causes 1ns latency, 31 stages causes 31ns latency compare to 20ns latency on northwood. Moreover, longer pipeline means a task can only be accomplished after 31 stages of pipeline, compare to 20 stages of northwood. Therefore, if no enhancement on cache, branch prediction or prefetching, 31 stages of pipeline will definitely slower than 20 stages pipeline CPU at the same clock speed. Main advantage of having long pipeline is to ramp up clock speed , because each task are divided into more stages, where each stage equal to 1 clock cycle.
charge-n-go
post Apr 12 2004, 06:11 PM

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The power of 100Watt ++ CPU tongue.gif

jarofclay, how u measure your PWM temperature?
charge-n-go
post Apr 21 2004, 12:29 AM

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QUOTE (ikanayam @ Apr 21 2004, 12:08 AM)
It does not really matter if the bus width is 128bit or 256bit. What is certain is the Prescott's L2 bandwith is HALF of the Northwood's.

Agree. Smaller bus width with sufficient clock speed can have a higher bandwidth compare to larger bus width but paired with low clock speed.

Bandwidth = Clock speed x bus width / 8 (unit is Bytes/second)

What's important is the bandwidth, which is to carry data from L2 cache into the pipeline.

 

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