lets say we have 2 ddr 400 which have timings like this
modul A 2-2-2-5 and
modul B 3-3-3-8
obviously the modul A will win because although both run at 400mhz,
but modul A CAS is 5, which means the data will be transfered after 5 complete clock cycle compared to modul B which needed 8 clock cycle b4 it can transfer data
p/s: correct me if there's any mistake.......blur2 abit already
Chow.
Sep 28 2006, 12:45 AM
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