Interesting article for Intel, Concerning chipset strap
|
|
 Aug 24 2006, 06:11 AM, updated 20y ago
Return to original view | Post
#1
|
 
VIP
3,773 posts Joined: Jan 2003 From: Anywhere lah...as long got Kopi-O   
|
Courtesy of Tony OCZ which helps a lot in terms of understanding how the chipsets work at OC'ed speeds and how to best work on it
The discussion: http://xtremesystems.org/forums/showthread.php?t=106834 The article: http://www.bleedinedge.com/forum/showthread.php?t=22297 Note the article is to be updated as Tony makes further progress sifting thru the white papers This post has been edited by almostthere: Aug 24 2006, 06:16 AM |
|
|
Sep 9 2006, 01:10 AM
Return to original view | Post
#2
|
|
VIP
3,773 posts Joined: Jan 2003 From: Anywhere lah...as long got Kopi-O
|
QUOTE(cks2k2 @ Sep 9 2006, 12:36 AM) Tony unlocks the reason why lower-end C2Ds can o/c more than the higher-end ones (and NO, it's not because of the cache). hehheeee...finally someone who did bother to read about it. But it follows the basic rule of FSB OC'ing. Lower multi's is the classic methodC2D o/c secrets  |
|
|
Sep 9 2006, 06:20 PM
Return to original view | Post
#3
|
|
VIP
3,773 posts Joined: Jan 2003 From: Anywhere lah...as long got Kopi-O
|
QUOTE(cks2k2 @ Sep 9 2006, 09:17 AM) Only up to a point: if the ratio btw std multiplier and set multiplier is too much x FSB the strain on the NB will limit the o/c. Which is where the article helps in understanding it's effects and the strap issues. |
| Change to: |  0.0154sec
 0.36
 6 queries
 GZIP Disabled
Time is now: 29th November 2025 - 07:07 PM |
Quote