Why..when i on stock...my memory bandwidth efficiency in sandra report on 68%? Even my timing was 6-3-3-2.5 with 1T command.
Then when i try Overclock 1:1 to get DDR500 at 2250mhz..My bandwidth Efficiency is now 74%
When i use 3:2 Doing DDR466 At 2600mhz...My bandwidth Efficiency is 82%.
Then When i increase my clock speed to max at 2.76ghz (306x9) 3:2 DDR500.,...i have bandwidth efficiency of 89% .

That on multiplier of 9.
Then i try use 325HTT * 8Multi (2600mhz) with 3:2 DDR520. I get again 82% .
Using another Divider at 4:3..i get the 82% still.

Conclusion: The clockspeed is proportional to bandwidth efficiency?
This is a problem to me as i was thinking to under volt my venice and run around at 2250mhz...but..only 74-75% efficiency of the ram.

Pls take note that all the test is done using the same timing.

Clockspeed do affects the bandwidth.

Same case like mine. Using 255mhz @ 3-4-4-10 and the efficiency is 93%.

If...opty run at 3.0ghz...sure the efficiency is high and dont need CL2.0 BH5 to overclock rite? Since the efficiency of the bandwidth is high enuff.

the CL2.0 for BH-5 is to make up for the mhz it loses compared to tccd

but yeah, amd64, just go for higher clock. u will get better results.

A64 3000+ @ 2007MHz@ 1.275V
2.5-3-2-7@1T@223Mhz
bandwidth efficiency 78%
i think its not dependent on clockspeed?

This post has been edited by jsnkok: May 3 2006, 09:52 PM

Try higher clockspeed with same RAM setting, that way you know the result whether CPU speed do affects or not.

Yea..it affect the speed . My first post was about Same Ram Timing/Option with Clock speed varies from default till 2.76ghz.



Anyway...if i put Drive Str Weak...for multiplier of 9, I will have 87% bandwidth efficiency no matter how high is my clock speed and Timing. Even 6-3-3-2.5 give same result like 9-5-5-3.0.
If my multiplier is 8x..it will stuck at 82% bandwidth efficiency. ALL this happen if Drive Str - WEAK. On the first post..it on Drive Str - Normal

The CPU actually issues memory read/write command after they have finished certain computations. That's y u can see higher CPU clock always leads to better efficiency.
I've noticed K8 architecture has more impact on efficiency when the CPU clock is increased. I suspect it's because the memory controller is built into CPU and follows the CPU clock. Higher clock = lower latency, bcoz Hz = 1/s.

just want to ask, except the dual channel supported then socket 939 and 754 has the same memory controller?

They have different memory controller giving different results eventough they are built onto the processor.

This post has been edited by uzairi: May 11 2006, 12:02 AM